XMRE in UVM 1.1

UVM
, ,
1

Hitting the following Cross module reference error:

Error-[XMRE] Cross-module reference resolution error
/home/sf10202/Labs.UVM/lab-project-10gEthernetMAC/testbench/verilog/testclass.sv, 32
Error found while trying to resolve cross-module reference.
token ‘tb_top’. Originating program ‘testcase’.
Source info: uvm_config_db::set(this, “env0.agent_rst.drv”, “vi_pkt_tx_if”,
tb_top.pkt_tx_if);

I’m trying to set virtual interface in reset agent’s driver with config_db set call. The actual interface instantiation is in top module tb_top :

packet_tx_interface pkt_tx_if(clk_156m25,reset_156m25_n);

All UVM classes are within testcase.sv:

program testcase();
   import uvm_pkg::*;

   `include "/home/sf10202/Labs.UVM/lab-project-10gEthernetMAC/testbench/verilog/testclass.sv"

   initial begin
      run_test();
   end
endprogram

And testclass has that configdb set call in build phase:

class test_base extends uvm_test;

`uvm_component_utils(test_base)

env env0;

   function new(input string name, input uvm_component parent);
        super.new(name,parent);
   endfunction


   virtual function void build_phase(input uvm_phase phase);
        super.build_phase(phase);
        env0 = env::type_id::create("env0",this);

        //run rst sequence on reset sequencer
        uvm_config_db#(uvm_object_wrapper)::set(this, "env0.agent_rst.seqr.reset_phase", "default_sequence" ,reset_sequence::get_type());

        //Connect virtual interface pkt_tx to actual interface in reset agent
        uvm_config_db#(virtual packet_tx_interface)::set(this, "env0.agent_rst.drv", "vi_pkt_tx_if", tb_top.pkt_tx_if);

Can someone help me fix this ?

2

In reply to alokchandarhs:

In your last set() call, you are trying to reference an interface in ‘tb_top’. As the error explains, it is illegal to refer to anything outside of the scope of the package.

The UVM Cookbook article on using the UVM Configuration Database demonstrates how to pass an interface from the testbench to the top-level test.

3

In reply to cgales:

I’m generating clocks, instantiating interfaces and instantiating dut in a module tb_top.

module tb_top();

/*AUTOREG*/
logic [7:0]     tx_buffer[0:10000];
integer         tx_length;
logic           clk_156m25;
logic           clk_312m50;
logic           clk_xgmii_rx;
logic           clk_xgmii_tx;
logic           reset_156m25_n;
logic           reset_xgmii_rx_n;
logic           reset_xgmii_tx_n;

integer       tx_count;
integer       rx_count;

.
.
.
packet_tx_interface pkt_tx_if(clk_156m25,reset_156m25_n);
.
.
.
xge_mac dut(
.
.
.
);

Module tb_top gets compiled along with testcase in makefile.

Since the instantiation is done in tb_top, I want to refer to that from within program, is that not allowed ?

I have actually accessed interface in this fashion in another example where it works perfectly fine:

Example 2 where this method works:

testclass.sv

`include "reset_sequence.sv"
`include "packet_sequence.sv"
`include "env.sv"


class test_base extends uvm_test;
env envo;
packet_sequence seq;
  `uvm_component_utils(test_base);

   function new(input string name="Base test", input uvm_component parent);
     super.new(name,parent);
   endfunction



 virtual function void start_of_simulation_phase(input uvm_phase phase);
   super.start_of_simulation_phase(phase);
   uvm_top.print_topology();
   factory.print();
  endfunction

 virtual function void build_phase(input uvm_phase phase);
        super.build_phase(phase);
        envo = env::type_id::create("envo",this);

        //Running packet seq on packet sequencer using config_db
        uvm_config_db#(uvm_object_wrapper)::set(this, "envo.agent_in.p_seqr.main_phase", "default_sequence", packet_sequence::get_type() );

        //Running reset seq on rst sequencer using config_db
        uvm_config_db#(uvm_object_wrapper)::set(this, "envo.agent_rst.p_seqr.reset_phase", "default_sequence", reset_sequence::get_type() );

        //Connecting virtual interface vi in input agent to actual interface riff
        uvm_config_db#(virtual router_interface)::set(this, "envo.agent_in.drv", "vi", router_test_top.riff);

Here router_test_top is module, whereas testclass gets included in testcase. Testcase in this example 2 is same as earlier.

router_test_top

module router_test_top();

   bit          clk;
   logic        reset_n;

   //Clock generator
   always #5 clk = ~clk;

//   initial begin
//      reset_n = 1'b1;
//      @(posedge clk); reset_n = 1'b0;
//      @(posedge clk); reset_n = 1'b1;
//   end

   //Instantiate Router Interface
   router_interface riff(clk, reset_n);
   //router_interface riff(clk);

   //Instantiate DUT
   switch switch0 (.clk         (clk            ),      //input
                .reset_n        (riff.reset_n   ),      //input
                .src_addr       (riff.src_addr  ),      //input
                .src_data       (riff.src_data  ),      //input

                .dst_addr       (riff.dst_addr  ),      //output
                .dst_data       (riff.dst_data  )       //output
               );

   initial begin
      $vcdpluson();
   end

endmodule