How to write a assertion to check if the clock is running before a bus or signal sees a change

SystemVerilog
, ,
1

module reqServer( input clk, input reset, input [1:0] reqBus);

Consider the above interface. I want to make sure that reqBus changes only when the clk is running. Say reqBus changes from 1 to 2 or 2 to 0, clock must have been running prior to that change if not flag an assertion.

2

In reply to Sai Raghavendran :

You could keep a log in a module variable of the time of clk transition.
At a Change od req, test that the current time is within range of the last clk.


realtime t:
let limit=10ns;
always @(posedge clk t <=$realtime;
ap_req: assert property(@($change(reqbus) 
      $realtime-t <= limit);

Ben Cohen
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Is the limit here the frequency of the clock ?

4

In reply to Sai Raghavendran :
let limit=10ns;
ap_req: assert property(@($change(reqbus)
$realtime-t <= limit); // limit is the period of the clock
t is sampled, thus if the clock period is 10ns and $change(reqbus) occurred on a clocking event at time 1010ns then the assertion checks that there was a clocking event at tome 1000ns.
The assertion would fail if the clock stopped at t=200ns and then restarted at t=1010ns.
Thus, for the assertion to work, you would have to assume that the clock was running one cycle before the change of reqbus.