Verification Academy

Topic	Replies	Views	Activity
Object handles and randomization SystemVerilog SystemVerilog , constraint , constraint-randomization	11	7101	September 15, 2022
Constraint Problem SystemVerilog SystemVerilog	2	570	September 15, 2022
Creating array of coverpoints to take coverage of a bus Coverage Coverage	4	757	September 14, 2022
Starting of sequence UVM UVM	2	560	September 14, 2022
Assertion to check real value SystemVerilog SystemVerilog , SVA	2	796	September 14, 2022
Uvm_config_db set from module, get from testcase? UVM UVM , uvm-uvm_config_db-module-class	9	1185	September 13, 2022
Reg_field.configure(..volatile()); UVM UVM	6	5354	September 13, 2022
$value$plusargs string input with spaces SystemVerilog SystemVerilog	1	464	September 13, 2022
How to map a string to a hierarhical circuit net? SystemVerilog SystemVerilog , dpi-c , systemverilog-Strings	2	660	September 13, 2022
How to reuse the configuration/initial state cycle across tests? UVM UVM , resuse-of-initial-cycles	1	367	September 12, 2022
Multiple scoreboards in UVM TB framework UVM UVM , testbench , UVM-scoreboard	3	1212	September 12, 2022
$urandom_range randomizes a value out of given range SystemVerilog SystemVerilog , urandom_range	1	605	September 12, 2022
Simulation not going forward if i use delay for each randomize of class object SystemVerilog SystemVerilog , why-randomization-not-happening-in-case-of-delay-posedge-clk-	2	411	September 11, 2022
Difference between Packed and UnPacked Arrays OVM OVM	8	100245	September 11, 2022
How can I print the hierarchy of the UVM RAL? UVM UVM , uvm_ral	1	756	September 10, 2022
Big-endian and Little-endian SystemVerilog SystemVerilog , Big-endian-and-Little-endian	1	2369	September 10, 2022
UVM Driver needs to do 100(`MAX_TRANS) transactions in which the address needs to transfer every posedge clock cycle and the data needs to transfer every four cycles(`MAX_WAIT). I tried the below sample code, but didn't get it to work UVM UVM , assertion , package-variable-uvm	3	771	September 10, 2022
Attempting to reserve info from uvm mem mam UVM UVM	0	321	September 9, 2022
What is the parameter type for the sequence class? Is it the name of the data_transaction class or the handle to the class? UVM UVM , uvm-sequence-item	2	552	September 8, 2022
Transition Coverage for multiple write port data Coverage Coverage , transition-coverage-cross-bins-ignore_bins , system-verilog-coverage-with-clause-coverpoints , systemverilog-coverage	0	498	September 8, 2022
Uvm_config_db#(color_t)::set(this, "driver, "font_color", CYAN); UVM UVM , uvm_config_db , uvm_color	2	570	September 8, 2022
SE: SystemVerilog keyword 'class' is not expected to be used in this context SystemVerilog SystemVerilog , class-not-expected-to-use-in-this-context	3	2415	September 8, 2022
Are get_next_item() and item_done() inbuilt methods of the uvm_seq_item_pull_port or do they require to be defined somewhere? UVM UVM , uvm-uvm_driver-	1	461	September 8, 2022
A race condition between threads concurrently accessing the register model UVM UVM , RAL-UVM	1	622	September 8, 2022
How to disable fork join or fork join_any after executed particular thread or process, please look at example SystemVerilog SystemVerilog , assertion , System-Verilog	5	892	September 8, 2022
Can I extend uvm_driver hieracial like uvm_driver > base_driver > my_driver? UVM UVM	2	403	September 8, 2022
Segmenting fault error SystemVerilog SystemVerilog , segment-fault-dpi	1	903	September 7, 2022
Two variable based transition covrage Coverage SystemVerilog , Coverage , Coverage-bins , transition-coverage-cross-bins-ignore_bins	1	591	September 6, 2022
Implication and followed by operators SystemVerilog SystemVerilog , SVA	1	596	September 6, 2022
Uvm_reg: UVM_WARNING: Setting the value of field "xxx" while containing register xxxx is being accessed may result in loss of desired field value UVM UVM , UVM_REG-RACE-CONDITION	6	5012	September 6, 2022