$urandom_range randomizes a value out of given range

SystemVerilog
,
1

Hi,
I’m writing a test, and I try to randomize a value in given range using $urandom_range as following:


bit [6:0] long_hyst_val;
bit [6:0] short_hyst_val;
bit [6:0] hyst_val;
int unsigned long_max = 128;
int unsigned long_min = 90;
int unsigned short_max = 15;
int unsigned short_min = 5;

function void define_hyst_val();
    long_hyst_val = $urandom_range(long_max, long_min);
    short_hyst_val = $urandom_range(short_max, short_min);
    hyst_val = $urandom_range(1,0) ? long_hyst_val : short_hyst_val;
endfunction

This function is called in a loop multiple times, and at the last iteration I see that the “hyst_val” var takes the value of “long_hyst_val”, which randomized value is ‘0’.
I looked it up in the SV LRM, tried multiple things but without any success.
Would appreciate some help here, thanks!

2

In reply to Noe Touaty:

With a few more lines of code, you could have provided a complete example as below:


module testbench();
  bit [6:0] long_hyst_val;
  bit [6:0] short_hyst_val;
  bit [6:0] hyst_val;

  int unsigned long_max = 128;
  int unsigned long_min = 90;
  int unsigned short_max = 15;
  int unsigned short_min = 5;
 
  function void define_hyst_val();
    long_hyst_val = $urandom_range(long_max, long_min);
    short_hyst_val = $urandom_range(short_max, short_min);
    hyst_val = $urandom_range(1,0) ? long_hyst_val : short_hyst_val;
  endfunction
  
  initial begin
    repeat (20) begin
      define_hyst_val();
      $display("long_hyst_val is %d", long_hyst_val);
      $display("short_hyst_val is %d", short_hyst_val);
      $display("hyst_val is %d", hyst_val);
    end
  end
  
endmodule

Your problem is that a value of 128 for long_max requires 8 bits, but your signals are only 7 bits.