Verification Academy

Topic	Replies	Views	Activity
Assertion property for busarbiter reset SystemVerilog SystemVerilog	1	296	December 3, 2022
SystemVerilog Preprocessing Engine SystemVerilog SystemVerilog , SystemVerilog-preprocessor	2	604	December 3, 2022
Separate logfiles for checkers SystemVerilog SystemVerilog	1	343	December 2, 2022
How does "ref" only have benefit for large data structures? SystemVerilog SystemVerilog	3	535	December 2, 2022
How does uvm_component go to Clean-up phases from Run_phases? UVM UVM , run_phase , uvm_component , phase_raise_objection	6	1088	December 2, 2022
Changing initial value of an internal DUT signal from SystemVerilog class UVM UVM , SystemVerilog-force , DUT-internal-signal , SV-interface-bind-to-vhdl	1	450	December 2, 2022
Need information on AXI transaction compare method usage UVM UVM	1	489	December 1, 2022
Why does declaration and initialization of an automatic variable after allocation of dynamic array with a task fail compilation? SystemVerilog SystemVerilog , dynamic-arrays , tasks , automatic-variables , dynamic-array-memory-allocation , task-syntax	1	656	December 1, 2022
All Values of a coverpoint need to be hit at same time SystemVerilog SystemVerilog , Coverage-bins , coverpoint-sample , array-covergroup-functional-coverage , system-verilog-coverage-with-clause-coverpoints , coverage-optiongoal-optionweight-goal-weight	6	1073	November 30, 2022
Extracting a number from a string in system verilog SystemVerilog SystemVerilog , systemverilog-Strings	5	6056	November 30, 2022
Constraint for 5 bits set and consecutively set for 80% of the time SystemVerilog SystemVerilog , constraint-randomization	19	2114	November 30, 2022
Correct property to count an event until another event happens SystemVerilog SystemVerilog , System-Verilog , SVA , assert-property	11	1314	November 29, 2022
Assertion : ClkGate state and TransactionCount assertion SystemVerilog SystemVerilog , assertion	6	916	November 29, 2022
Verilog code confusion, I do not understand this line of code SystemVerilog SystemVerilog , assign , logical-equality , logical-AND , current-value	4	682	November 29, 2022
Assertion for check SOP signal loss SystemVerilog SystemVerilog , assertion	8	1341	November 28, 2022
Parameterized class declaration in UVM UVM UVM	1	358	November 28, 2022
System verilog assertion on asynchronous signal that kept calibrated SystemVerilog SystemVerilog , assertion , SVA	3	1113	November 28, 2022
Trying to read hex data from a file SystemVerilog SystemVerilog , fread-fscanf-file	4	2584	November 27, 2022
Check problem SystemVerilog SystemVerilog	3	711	November 26, 2022
What difference between @event and wait (event.triggered)? UVM UVM , event	14	53502	November 25, 2022
Loops inside Function new in OVM OVM OVM , function-new , Cookbook-OVMPhasing	5	4004	November 25, 2022
Usage of local parameter in a class SystemVerilog SystemVerilog , parameter	1	708	November 25, 2022
Error-[SE] Syntax error Following verilog source has syntax error : "abstract12.sv", 44: token is '\037777777742' $display(\037777777742\037777777600\037777777634Derived packet is :%p\037777777742\037777777600\037777777635,type_var); SystemVerilog SystemVerilog	1	1503	November 25, 2022
Regarding ' with ' clause for Transition bins Coverage Coverage , Regarding--with--clause-for-Transition-bins	4	815	November 25, 2022
Can I pause a for loop? SystemVerilog SystemVerilog	4	610	November 24, 2022
Overriding the time consuming phases in UVM by calling super method UVM UVM , run_phase	1	493	November 24, 2022
Ignore bins with transition (wit iff condition) Coverage Coverage , Coverage-bins , transition-coverage-cross-bins-ignore_bins , ignore-bins	1	655	November 24, 2022
Probability on Constraint in SystemVerilog SystemVerilog SystemVerilog , rand-constraint	6	1363	November 24, 2022
Not able to define a function in interface and call it from Class UVM UVM , calling-a-function-defined-in-interface	3	700	November 24, 2022
Pattern generation SystemVerilog SystemVerilog	1	474	November 23, 2022

Assertion property for busarbiter reset

SystemVerilog

1

296

December 3, 2022

SystemVerilog Preprocessing Engine

SystemVerilog

SystemVerilog , SystemVerilog-preprocessor

2

604

December 3, 2022

Separate logfiles for checkers

SystemVerilog

1

343

December 2, 2022

How does "ref" only have benefit for large data structures?

SystemVerilog

3

535

December 2, 2022

How does uvm_component go to Clean-up phases from Run_phases?

UVM

UVM , run_phase , uvm_component , phase_raise_objection

6

1088

December 2, 2022

Changing initial value of an internal DUT signal from SystemVerilog class

UVM

UVM , SystemVerilog-force , DUT-internal-signal , SV-interface-bind-to-vhdl

1

450

December 2, 2022

Need information on AXI transaction compare method usage

UVM

1

489

December 1, 2022

Why does declaration and initialization of an automatic variable after allocation of dynamic array with a task fail compilation?

SystemVerilog

SystemVerilog , dynamic-arrays , tasks , automatic-variables , dynamic-array-memory-allocation , task-syntax

1

656

December 1, 2022

All Values of a coverpoint need to be hit at same time

SystemVerilog

SystemVerilog , Coverage-bins , coverpoint-sample , array-covergroup-functional-coverage , system-verilog-coverage-with-clause-coverpoints , coverage-optiongoal-optionweight-goal-weight