All Values of a coverpoint need to be hit at same time

SystemVerilog
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1

Hi,

I have a scenario where I have 3 opcodes and a 4 bit ID. How do I write a coverpoint for the scenario where I want to check for cases,
Same Opcode with 16 ID’s
Diff Opcode with 16 ID’s.
So, in simple terms, I want to have all 16 ID’s active at the same time with the same opcode and different opcode.

If it is not at the same time, then we can have separate bins written for 16 ID’s and have a cross with the opcodes using with/iff condition, but how do I write for Same time condition ?

Thanks

2

In reply to Thirumal:

Could you write a few lines of code, please?
It isn’t easy to get what you wrote.
As far as I observed, your question looks like this -


bit [3:0] id;
covergroup g;
a: coverpoint id{.......} //opcode_1
b: coverpoint id{.......} //opcode_2
c: coverpoint id{.......} //opcode_3
endgroup

Now you want to combine these three opcodes.
Am I right?

3

Thanks Shubhabrata for the reply.
I think you got it in a different way. Let me make it clear.

bit [3:0] id;
typedef enum[1:0] {ADD, SUB,MUL} opcode_type;
opcode_type opcode;
covergroup g;

// Same and Diff opcodes means back to back same and diff opcodes.
Same_opcode_with_all_16_ids_at_same_time : coverpoint id { bins id_0= {0} with (opcode_prev= opcode);
......
bins id_15 = {15} with (opcode_prev = opcode);

Diff_opcode_with_all_16_ids_at_same_time : coverpoint id { bins id_0= {0} with (opcode_prev != opcode);
......
bins id_15 = {15} with (opcode_prev != opcode);


endgroup

//sampling the cg

This might work but this is not what we expect. All the bins we define may hit once or many a times in the entire simulation time but we want all of them to hit at the same time.

Thanks

4

In reply to Thirumal:
I believe you have the following requirement ::


  typedef enum  bit [1:0] {ADD, SUB,MUL , DIV} opcode_type; // Missing keyword  ' bit ' above 
  
  opcode_type opcode; 

   covergroup  gc ;  //  sample()  Must  be  called
   
     same:coverpoint opcode
     {
        bins id_0  =  ( ADD => ADD ) ;
        bins id_1  =  ( SUB => SUB ) ;
        bins id_2  =  ( MUL => MUL ) ;
        bins id_3  =  ( DIV => DIV ) ;
     }
     
     diff:coverpoint opcode
     {
        bins id_0  =  ( ADD => [ SUB : DIV ] ) ;
        bins id_1  =  ( SUB =>  ADD ) , ( SUB => [ MUL : DIV ] ) ;  // 3 transitions covered by single bin 
        bins id_2  =  ( MUL => [ ADD : SUB ] ) , ( MUL => DIV ) ;   // 3 transitions covered by single bin 
        bins id_3  =  ( DIV => [ ADD : MUL ] ) ;
     }

   endgroup

All the bins we define may hit once or many a times in the entire simulation time but we want all of them to hit at the same time.

I am not clear on this . At a particular time how can a transaction have ALL opcodes at once ? It’s 4-bit type so can have only 1 value at a time .

For the above code only 1 bin out of the 8 can he hit at a particular time .

**You could also merge the 4 bins within each coverpoint to a single bin but that would give you total of 2 bins ( 1 within each coverpoint ) .
Even in that case only 1 out of 2 bins would be covered at a time .
**

5

In reply to Thirumal:

A number of people including myself have trouble understanding your question. It might help to write a very small example that generate stimulus for the scenarios you want covered. It also might help to use different words or even multiple words for “same” and “time”.

6

Hi Dave,

The problem here is my DUT expects all of the 16 ID’s to be active/ Outstanding at the same time (at say 50ns simulation time) and all of the 16 ID’s are active at that time with same opcodes or different opcodes. The total number of opcodes are 3 here. We need to cover if all of the 16 id’s are active with same opcodes and different opcodes.
Does that makes sense now?

Thanks,
Thirumal

7

In reply to Thirumal:

No it does not. You keep repeating yourself using identical words. Write a very small execute example that generate stimulus for the scenarios you want covered. Then we might be able to define a covergroup for it.