Loops inside Function new in OVM

OVM
, ,
1

function new (string str=“pmc_svt_i2c_system_configuration”);
super.new(str);

num_slaves  = 128; // 128 new slaves
int i;
/** Create port configurations */
create_sub_cfgs(num_masters, num_slaves);


  for(i=32'h20 ; i < 32'h60 ; i ++) begin
     slave_cfg[i].is_active         = 0;
     slave_cfg[i].slave_address     = i[9:0]; // `SVT_I2C_SLAVE0_ADDRESS; 
     slave_cfg[i].bus_speed         = HIGHSPEED_MODE;
     slave_cfg[i].enable_10bit_addr = 0;
  end

endfunction

On compiling the above code, the following error is thrown.

Error-[SE] Syntax error
Following verilog source has syntax error :
“/nfs/fm/disks/001/config.sv”,
22: token is ‘int’
int i;
^
System verilog keyword ‘int’ is not expected to be used in this context.

Why can’t we use the variable int or bit in the function new?

2

In reply to Siva Namathoti:

You can, but SystemVerilog requires all variable declarations precede all procedural code. The statement ‘num_slaves = 128;’ is procedural, so declaring ‘int i’ can not come after it. Move the declaration of ‘i’ to the top of the function.

3

In reply to cgales:
You also move the declaration of ‘I’ as part of the for loop statement. Then it becomes a local variable to the for loop block.

for(int i=32'h20 ; i < 32'h60 ; i ++) begin
4

In reply to cgales:
This might sound very silly question but anyway…
How num_slaves =128 is procedural code?

5

In reply to Abuzar Gaffari:

Function , task , initial are procedural blocks .

Constructor ( new ) is a function so statements written within them are procedural .

6

In reply to cgales:

Since SystemVerilog allows user to declare variables within begin … end block
the variable i could be also defined as following right ? ::


function new (string str="pmc_svt_i2c_system_configuration");
  super.new(str);

  num_slaves = 128; // 128 new slaves
 
 begin  //  Added  to  declare  variable(s)  
   int i;
   //  Remaining  code  here
 end

endfunction