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October 2019

Why Reset Domain Crossing Verification is an Emerging Requirement
Questa Design Solutions Oct 01, 2019 Kurt Takara pdf

September 2019

Questa SLEC Fact Sheet
Formal Verification Sep 30, 2019 Nicolae Tusinschi link
Stimulus and Analysis Data Flow
UVM Framework Sep 09, 2019 Bob Oden Session
Stimulus and Analysis Data Flow
UVM Framework Sep 09, 2019 Bob Oden pdf
Code Generation Guidelines
UVM Framework Sep 09, 2019 Bob Oden Session
Code Generation Guidelines
UVM Framework Sep 09, 2019 Jonathan Craft pdf

August 2019

Machine-Learning-Assisted Agile VLSI Design for Machine Learning
Machine Learning Aug 31, 2019 Brucek Khailany link
Assuring the Integrity of RISC-V Cores and SoCs
Formal Verification Aug 21, 2019 Nicolae Tusinschi pdf
A New Approach to Low Power Verification - Power Aware Apps
Low Power Aug 21, 2019 Madhur Bhargava pdf
A New Approach to Low-Power Verification: Power Aware Apps
Low Power Aug 21, 2019 Madhur Bhargava Paper
Coverage Driven Verification of NVMe Using Questa VIP
Verification IP Aug 21, 2019 pdf
Using HLS to Accelerate Computer Vision for Autonomous Drive
High-Level Synthesis Aug 20, 2019 pdf
Source Code Download: Fun with UVM Sequences - Coding and Debugging
Standards Aug 20, 2019 tar
Unraveling the Complexities of Functional Coverage - An Advanced Guide to Simplify Use Models
Coverage Aug 02, 2019 Thomas Ellis pdf
Technical Paper: Moving Beyond Assertions - An Innovative Approach to Low-Power Checking Using UPF Tcl Apps
Standards Aug 02, 2019 pdf
Technical Paper: UVM IEEE Shiny Object
Standards Aug 02, 2019 pdf
Technical Paper: Results Checking Strategies with Portable Stimulus
Standards Aug 02, 2019 pdf
Technical Paper: Transaction Recording Anywhere Anytime
Standards Aug 02, 2019 pdf
Improving Verification Predictability and Efficiency Using Big Data
Planning, Measurement and Analysis Aug 02, 2019 Darron May pdf

July 2019

Visualizer™ Debug Environment: Class-based Testbench Debugging using a New School Debugger – Debug This!
Simulation Jul 17, 2019 Rich Edelman Article
Is It Magic, or Ingenious People Working with Remarkably Advanced Technology?
Simulation Jul 16, 2019 Verification Horizons Article
An Emulation Strategy for AI and ML Designs
Machine Learning Jul 15, 2019 Vijay Chobisa pdf
Deep Learning Accelerator Using HLS
High-Level Synthesis Jul 15, 2019 pdf
DAC 2019 Academy PDF Presentation: Methodology to Debug Real Number Model (RNM) Boundary Scenarios using Symphony & Visualizer
Standards Jul 15, 2019 pdf
DAC 2019 Academy PDF Presentation: What's Missing and What Should Be Next for SystemVerilog
Standards Jul 15, 2019 pdf

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

Browse all content in Siemens Verification Academy with the tag rtl emulation

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