Hi ,
I have two clock with different frequency. I need to check if both the clock are aligned with each other.
If I use sva implication operator , it will evaluate the condition in next clock cycle , but I need evaluation should happen in same clock.
Please help in writing the assertion.
Regards,
Sidharth
In reply to sidharth.sankar77:
I have two clock with different frequency. I need to check if both the clock are aligned with each other.
If I use sva implication operator , it will evaluate the condition in next clock cycle , but I need evaluation should happen in same clock. Please help in writing the assertion.
SVA will not work because of the sampling regions. The following solution does work.
Basically, at the the clock edges of clk1 and clk2 you record the current time at which these occurrences happen.
always @(posedge clk1) tclk1=$realtime;
always @(posedge clk2) tclk2=$realtime;
Assuming that the clocks are within a certain range, you wait for that time range and check if those recorded times are within acceptable ranges.
always @(posedge clk1) begin
automatic realtime delta;
#3 delta=tclk1-tclk2 > limit;
if(delta) `uvm_error("clk1_to_clk2",
$sformatf("%m : Limit error clk1 to clk2, %t", delta));
end
The following testbench demonstrates the concept and simulation run. You may need to tune the timeunit/precision and the acceptable limits.
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
timeunit 10ps; timeprecision 1ps;
bit clk1, clk2;
int jit=10;
realtime limit=100ps, tclk1, tclk2, jitter=10ns;
initial forever #1000 clk1=!clk1;
initial forever begin
#jitter; $display("jitter = $t", jitter); clk2=!clk2;
end
initial begin
$timeformat(-9, 1, " ns", 8);
$display("%t", $realtime);
end
always @(posedge clk1) tclk1=$realtime;
always @(posedge clk2) tclk2=$realtime;
always @(posedge clk1) begin
automatic realtime delta;
#3 delta=tclk1-tclk2 > limit;
if(delta) `uvm_error("clk1_to_clk2",
$sformatf("%m : Limit error clk1 to clk2, %t", delta));
end
always @(posedge clk2) begin
automatic realtime delta;
#3 delta=tclk2-tclk1 > limit;
if(delta) `uvm_error("clk2_to_clk1",
$sformatf("%m : Limit error clk2 to clk1, %t", delta));
end
/* The following DOES NOT WORK BECAUSE OF SVA SAMPLING REGIONS
ap_rose_clk1_clk2: assert property(@(posedge clk1) $rose(clk2));
ap_rose_clk2_clk1: assert property(@(posedge clk2) $rose(clk1));
ap_fell_clk1_clk2: assert property(@(negedge clk1) $fell(clk2));
ap_fell_clk2_clk1: assert property(@(negedge clk2) $fell(clk1)); */
initial begin
$timeformat(-12, 1, "ps", 8);
repeat(2000) begin
@(posedge clk1);
if (!randomize(jit) with
{ jit dist {10:=1, 9:=1, 11 :=1};
}) `uvm_error("MYERR", "This is a randomize error")
jitter=10ns + jit*1ps;
end
//$stop;
end
endmodule
// simulation
0.0 ns
# jitter = $t1000
# jitter = $t1000.9
# jitter = $t1001.1
# jitter = $t1001.1
# UVM_ERROR .\clk1toclk2.sv(23) @ 50030.0ps: reporter [clk1_to_clk2] top : Limit error clk1 to clk2, 10.0ps
# jitter = $t1000.9
# jitter = $t1000.9
# UVM_ERROR .\clk1toclk2.sv(23) @ 70030.0ps: reporter [clk1_to_clk2] top : Limit error clk1 to clk2, 10.0ps
# jitter = $t1001
# jitter = $t1001
# UVM_ERROR .\clk1toclk2.sv(23) @ 90030.0ps: reporter [clk1_to_clk2] top : Limit error clk1 to clk2, 10.0ps
# jitter = $t1001
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
See Paper: VF Horizons:PAPER: SVA Alternative for Complex Assertions - SystemVerilog - Verification Academy
In reply to ben@SystemVerilog.us:
Thank Ben.
In reply to sidharth.sankar77:
Delta should be declared as type bit.
automatic bit delta; // realtime delta;
#3 delta=tclk2-tclk1 > limit;
Made the error because I initially used to store the delta time, but later used it in a comparison.
Glad you liked the solution. You may need to use the same approach the negedges of the 2 clocks.
Ben
In reply to ben@SystemVerilog.us:
Hi Ben,
Could you please let me i brief about
Thanks in advance
In reply to Mechanic:
See my reply at
https://verificationacademy.com/forums/systemverilog/sampling-point-assertions
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
In reply to ben@SystemVerilog.us:
Thanks for the informtion.
I would like to know can we write an assertion to check clock signal is toggling once the device if comes out of reset?
please guide me
Thanks in advance
In reply to Mechanic:
Measure the clock period.
Lots of discussion on this
https://verificationacademy.com/forums/systemverilog/checking-clock-period-using-system-verilog-assertion
https://verificationacademy.com/forums/systemverilog/assertion-check-pulses-clock
https://verificationacademy.com/forums/systemverilog/checking-clock-using-sva
also
property p_clk_hi;
realtime v;
@(posedge clk) (1, v=$realtime) |-> @(negedge clk) ($realtime-v)==300ns;
endproperty
ap_clk_hi: assert property(p_clk_hi);
property p_clk_lo;
realtime v;
@(negedge clk) (1, v=$time) |-> @(posedge clk) ($realtime-v)==700ns;
endproperty
ap_clk_lo: assert property(p_clk_lo);
In reply to ben@SystemVerilog.us:
Thanks Ben .
I understand how to verify the clock frequency,duty_cycle…
But the question is since the check is on clock itself how can we make sure whether the clock is available after the reset?since the check is on clock signal itself.how the ##1,|-> these operators will evaluate?
In the above example if the timing event istelf is not happened then assertion wont fire right?
In case of concurrent assertion everything fires based on the edge sensitive timing control.
Please let me know am i missing something .
Thanks in advance
In reply to Mechanic:
How can we make sure whether the clock is available after the reset?s
I suggest the use of a task with a fork join_any; one thread is a timeout, the other an edge of the clk (clk2 in my model below) That task is triggered periodically
task automatic t();
bit vclk=0;
if(rst_n) begin
fork
#35; // if ends first, then no clock
@(clk2) vclk=1'b1; // clk2 occurred
join_any
a_noclk: assert(vclk) else $display("@ %t no clocks", $realtime);
if(!vclk) -> e;
end
endtask
initial forever begin
#20 t();
end
Below is my testbench. You can use that approach to test for a keep-alive of the clock.
You need to adjust the delay values.
You can use the SVA assertions for the exact periods of the clocks.
See SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
bit clk, clk2, rst_n;
event e;
default clocking @(posedge clk); endclocking
initial
begin
#20 rst_n=1'b1;
#200;
forever #10 clk=!clk;
end
// how can we make sure whether the clock is available after the reset?s
task automatic t();
bit vclk=0;
if(rst_n) begin
fork
#35; // if ends first, then no clock
@(clk2) vclk=1'b1; // clk2 occurred
join_any
a_noclk: assert(vclk) else $display("@ %t no clocks", $realtime);
if(!vclk) -> e;
end
endtask
initial forever begin
#20 t();
end
// assertions here
initial begin
bit va, vb;
repeat(200) begin
repeat(1) @(posedge clk);
if (!randomize(clk2) with
{ clk2 dist {1'b1:=3, 1'b0:=1};
}) `uvm_error("MYERR", "This is a randomize error");
end
$stop;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
In reply to ben@SystemVerilog.us:
Thanks Ben.
Could you let me know is there any reason for the usage of the event e?
In reply to Mechanic:
For debug.
On concurrent assertions, tools may show the threads and pass/fail indications on the waveform, along with text messages. This model does not use concurrent assertions.
Since I like to debug using waveform views, the event tells me when the failures occur.