In reply to sidharth.sankar77:
I have two clock with different frequency. I need to check if both the clock are aligned with each other.
If I use sva implication operator , it will evaluate the condition in next clock cycle , but I need evaluation should happen in same clock. Please help in writing the assertion.
SVA will not work because of the sampling regions. The following solution does work.
Basically, at the the clock edges of clk1 and clk2 you record the current time at which these occurrences happen.
always @(posedge clk1) tclk1=$realtime;
always @(posedge clk2) tclk2=$realtime;
Assuming that the clocks are within a certain range, you wait for that time range and check if those recorded times are within acceptable ranges.
always @(posedge clk1) begin
automatic realtime delta;
#3 delta=tclk1-tclk2 > limit;
if(delta) `uvm_error("clk1_to_clk2",
$sformatf("%m : Limit error clk1 to clk2, %t", delta));
end
The following testbench demonstrates the concept and simulation run. You may need to tune the timeunit/precision and the acceptable limits.
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
timeunit 10ps; timeprecision 1ps;
bit clk1, clk2;
int jit=10;
realtime limit=100ps, tclk1, tclk2, jitter=10ns;
initial forever #1000 clk1=!clk1;
initial forever begin
#jitter; $display("jitter = $t", jitter); clk2=!clk2;
end
initial begin
$timeformat(-9, 1, " ns", 8);
$display("%t", $realtime);
end
always @(posedge clk1) tclk1=$realtime;
always @(posedge clk2) tclk2=$realtime;
always @(posedge clk1) begin
automatic realtime delta;
#3 delta=tclk1-tclk2 > limit;
if(delta) `uvm_error("clk1_to_clk2",
$sformatf("%m : Limit error clk1 to clk2, %t", delta));
end
always @(posedge clk2) begin
automatic realtime delta;
#3 delta=tclk2-tclk1 > limit;
if(delta) `uvm_error("clk2_to_clk1",
$sformatf("%m : Limit error clk2 to clk1, %t", delta));
end
/* The following DOES NOT WORK BECAUSE OF SVA SAMPLING REGIONS
ap_rose_clk1_clk2: assert property(@(posedge clk1) $rose(clk2));
ap_rose_clk2_clk1: assert property(@(posedge clk2) $rose(clk1));
ap_fell_clk1_clk2: assert property(@(negedge clk1) $fell(clk2));
ap_fell_clk2_clk1: assert property(@(negedge clk2) $fell(clk1)); */
initial begin
$timeformat(-12, 1, "ps", 8);
repeat(2000) begin
@(posedge clk1);
if (!randomize(jit) with
{ jit dist {10:=1, 9:=1, 11 :=1};
}) `uvm_error("MYERR", "This is a randomize error")
jitter=10ns + jit*1ps;
end
//$stop;
end
endmodule
// simulation
0.0 ns
# jitter = $t1000
# jitter = $t1000.9
# jitter = $t1001.1
# jitter = $t1001.1
# UVM_ERROR .\clk1toclk2.sv(23) @ 50030.0ps: reporter [clk1_to_clk2] top : Limit error clk1 to clk2, 10.0ps
# jitter = $t1000.9
# jitter = $t1000.9
# UVM_ERROR .\clk1toclk2.sv(23) @ 70030.0ps: reporter [clk1_to_clk2] top : Limit error clk1 to clk2, 10.0ps
# jitter = $t1001
# jitter = $t1001
# UVM_ERROR .\clk1toclk2.sv(23) @ 90030.0ps: reporter [clk1_to_clk2] top : Limit error clk1 to clk2, 10.0ps
# jitter = $t1001
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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