Assertion for checking clock alignment

SystemVerilog
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5

In reply to ben@SystemVerilog.us:

Hi Ben,

Could you please let me i brief about

  • The following DOES NOT WORK BECAUSE OF SVA SAMPLING REGIONS
    ap_rose_clk1_clk2: assert property(@(posedge clk1) $rose(clk2));
    ap_rose_clk2_clk1: assert property(@(posedge clk2) $rose(clk1));
    ap_fell_clk1_clk2: assert property(@(negedge clk1) $fell(clk2));
    ap_fell_clk2_clk1: assert property(@(negedge clk2) $fell(clk1)); */

Thanks in advance