In reply to ben@SystemVerilog.us:
Thanks Ben .
I understand how to verify the clock frequency,duty_cycle…
But the question is since the check is on clock itself how can we make sure whether the clock is available after the reset?since the check is on clock signal itself.how the ##1,|-> these operators will evaluate?
In the above example if the timing event istelf is not happened then assertion wont fire right?
In case of concurrent assertion everything fires based on the edge sensitive timing control.
Please let me know am i missing something .
Thanks in advance