Assertion for checking clock alignment

SystemVerilog
, ,
8

In reply to Mechanic:
Measure the clock period.
Lots of discussion on this
https://verificationacademy.com/forums/systemverilog/checking-clock-period-using-system-verilog-assertion

https://verificationacademy.com/forums/systemverilog/assertion-check-pulses-clock

https://verificationacademy.com/forums/systemverilog/checking-clock-using-sva

also


property p_clk_hi; 
	  realtime v; 
	  @(posedge clk) (1, v=$realtime) |-> @(negedge clk) ($realtime-v)==300ns;
	endproperty 
	ap_clk_hi: assert property(p_clk_hi);  
 
	property p_clk_lo; 
	  realtime v; 
	  @(negedge clk) (1, v=$time) |-> @(posedge clk) ($realtime-v)==700ns;
	endproperty 
    ap_clk_lo: assert property(p_clk_lo);