If there is a clock with frequency 1MHz and 30% duty cycle,how to check this clock if it has any glitches or not using System Verilog Assertions (SVA)?
In reply to perumallatarun:
If there is a clock with frequency 1MHz and 30% duty cycle,how to check this clock if it has any glitches or not using System Verilog Assertions (SVA)?
The following solution works, and includes a testbench. That testbench follows the style demonstrated in my 4th edition SVA book regarding verifying assertions.
import uvm_pkg::*; `include "uvm_macros.svh"
module m;
bit clk=1, a;
bit[0:1] t;
default clocking @(posedge clk); endclocking
initial forever begin
#298 if (!randomize(t) with
{ t dist {1'b1:=1, 1'b0:=10};
}) `uvm_error("MYERR", "This is a randomize error")
if(t) begin
clk=!clk;
#1ns clk=!clk;
#1ns clk=!clk;
end
else #2ns clk=!clk;
#398 if (!randomize(t) with
{ t dist {1'b1:=1, 1'b0:=10};
}) `uvm_error("MYERR", "This is a randomize error")
if(t) begin
clk=!clk;
#1ns clk=!clk;
#1ns;
end
else #2ns;
#300 clk=!clk;
end
property p_clk_hi;
time v;
@(posedge clk) (1, v=$time) |-> @(negedge clk) ($time-v)==300ns;
endproperty
ap_clk_hi: assert property(p_clk_hi);
property p_clk_lo;
time v;
@(negedge clk) (1, v=$time) |-> @(posedge clk) ($time-v)==700ns;
endproperty
ap_clk_lo: assert property(p_clk_lo);
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
In reply to ben@SystemVerilog.us:
Hi Ben,
Don’t you think it is better to use realtime instead of time datatype?
I feel that realtime allows one to reuse of assertions for gate-level simulations.
In reply to chitlesh:
In reply to ben@SystemVerilog.us:
Hi Ben,
Don’t you think it is better to use realtime instead of time datatype?
I feel that realtime allows one to reuse of assertions for gate-level simulations.
Yes, realtime is better.
property p_clk_hi;
realtime v;
@(posedge clk) (1, v=$realtime) |-> @(negedge clk) ($realtime-v)==300ns;
endproperty
ap_clk_hi: assert property(p_clk_hi);
property p_clk_lo;
realtime v;
@(negedge clk) (1, v=$time) |-> @(posedge clk) ($realtime-v)==700ns;
endproperty
ap_clk_lo: assert property(p_clk_lo);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
In reply to ben@SystemVerilog.us:
Hi Ben,
Is there any chance to write SVA for clock to check the frequency “inside an interface”.
Here we cannot use $real_time in interface, How to overcome this problem?.
Srikanth.
In reply to srikanth_manukonda:
What is so special about an interface that make you think you can’t use $realtime?
In reply to ben@SystemVerilog.us:
Be careful using equality with real numbers. See Comparing Floating Point Numbers, 2012 Edition | Random ASCII – tech blog of Bruce Dawson
In reply to dave_59:
I am facing compilation errors while using $real_time inside interface.
Error : cannot use real type in dynamic world
-Srikanth
In reply to srikanth_manukonda:
Please show some code and the exact error message. That error message seems strange.
In reply to srikanth_manukonda:
In reply to dave_59:
I am facing compilation errors while using $real_time inside interface.
Error : cannot use real type in dynamic world -Srikanth
As Dave pointed out, there are no restrictions on using the “$realtime” in interfaces.
BTW, $realtime is spelled without the “_”; you have $real_time, which is in error.
Maybe that is your issue.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
In reply to ben@SystemVerilog.us:
Hi Ben/Dave,
Do you guys personally think it’s better idea to check clock using property assertion ? I think the assertion will always be active through out the simulation. That will affect performance of the simulation time?
Just curious to know your views on same.
Thanks,
Digesh
In reply to Digesh:
Do you guys personally think it’s better idea to check clock using property assertion ? I think the assertion will always be active through out the simulation. That will affect performance of the simulation time?
- A concurrent assertion can be expressed with always and logic statements; thus, I don’t believe it would consume more simulation time than verification logic.
- As far as assertions always being active throughout the simulation, one can tailor the ON/OFF time of that verification logic (e.g., assertions or plain logic) via various techniques:
- 3. $asserton, $assertoff
4. initial statement with a defined number of repeats if needed
5. process kill, fork/join, etc.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
How can the same problem be handled using SVA but verifying with a formal checker tool and not in simulations?
Thanks,
Kanthi