In reply to Mechanic:
How can we make sure whether the clock is available after the reset?s
I suggest the use of a task with a fork join_any; one thread is a timeout, the other an edge of the clk (clk2 in my model below) That task is triggered periodically
task automatic t();
bit vclk=0;
if(rst_n) begin
fork
#35; // if ends first, then no clock
@(clk2) vclk=1'b1; // clk2 occurred
join_any
a_noclk: assert(vclk) else $display("@ %t no clocks", $realtime);
if(!vclk) -> e;
end
endtask
initial forever begin
#20 t();
end
Below is my testbench. You can use that approach to test for a keep-alive of the clock.
You need to adjust the delay values.
You can use the SVA assertions for the exact periods of the clocks.
See SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
bit clk, clk2, rst_n;
event e;
default clocking @(posedge clk); endclocking
initial
begin
#20 rst_n=1'b1;
#200;
forever #10 clk=!clk;
end
// how can we make sure whether the clock is available after the reset?s
task automatic t();
bit vclk=0;
if(rst_n) begin
fork
#35; // if ends first, then no clock
@(clk2) vclk=1'b1; // clk2 occurred
join_any
a_noclk: assert(vclk) else $display("@ %t no clocks", $realtime);
if(!vclk) -> e;
end
endtask
initial forever begin
#20 t();
end
// assertions here
initial begin
bit va, vb;
repeat(200) begin
repeat(1) @(posedge clk);
if (!randomize(clk2) with
{ clk2 dist {1'b1:=3, 1'b0:=1};
}) `uvm_error("MYERR", "This is a randomize error");
end
$stop;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
- SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA: Package for dynamic and range delays and repeats | Verification Academy
- SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy