Verification Academy

Topic	Replies	Views	Activity
Region scheduling between active and NBA SystemVerilog SystemVerilog , scheduling-semantcs	1	714	March 3, 2022
Parameterized function/task SystemVerilog SystemVerilog , parameterized-functiontask	1	916	March 2, 2022
Problem about assign UVM UVM	1	486	March 2, 2022
How to verify a DUT with master interface UVM UVM , APB-master-DUT	2	1009	March 1, 2022
Randomization Query SystemVerilog SystemVerilog	3	802	March 1, 2022
How to avoid "Too few instance port connections" error? SystemVerilog SystemVerilog , module , instance , Build-in-module , too-few-port-connections , module-instantiation	1	2690	March 1, 2022
FATAL error in config_db while trying to get object in sequence UVM UVM , systemverilog-uvm , RAL-UVM	1	1085	February 28, 2022
Disable fork label does not disable the thread SystemVerilog SystemVerilog , disable-fork , fork-join-_none , fork_join , disable-label	4	7540	October 16, 2025
Assertion to Check State Machine transitions in specified manner SystemVerilog SystemVerilog , Assertion-to-Check-State-Machine-transitions-in-specified-manner	1	2463	February 26, 2022
CROSS Coverage Coverage Coverage , cross-coverage , binsof , cross-bins	3	1140	February 26, 2022
Array constraint. Each row total should be 100, with each element less than 80. I want to understand how to do this using only sum method of array SystemVerilog SystemVerilog , constraint-randomization , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays	9	1870	February 25, 2022
Working with Multi-dimensional uvm_queue UVM UVM	3	1104	February 24, 2022
M_sequencer usage in start() UVM UVM , Start , m_sequencer	2	899	February 24, 2022
UVM register fields values coverage is not performed on current configuration data UVM UVM , UVM-reg-field-coverage-sample	0	517	February 24, 2022
Expression bit length determination with cast SystemVerilog SystemVerilog , System-Verilog , cast	2	1070	February 24, 2022
What is the usage of &&& operator in system verilog? SystemVerilog SystemVerilog	1	2733	February 23, 2022
Passing Unpacked Array of Packed Array as task arguments SystemVerilog SystemVerilog , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays	1	1354	February 23, 2022
Why in uvm only build phase having super.build phase,for connect phase why we didnt use super.connect phase? UVM UVM	3	1997	February 23, 2022
UVM RAL for configuration of TB in a SoC environment UVM UVM , Systemverilog-UVM-RAL	3	1197	February 23, 2022
Functions inside apb adapter are not being called from the test sequence UVM UVM , RAL , RAL-UVM , uvmral	2	774	February 23, 2022
State of the sequence after it has been killed UVM UVM	11	2032	February 22, 2022
UVM REG odd report messages UVM UVM	0	492	February 22, 2022
Alternative of "with" for transition Coverage Coverage Coverage	1	563	February 22, 2022
Call class function for properties Or any alternative to achieve? SystemVerilog SystemVerilog , constraint-randomization , Formal-Verification , assume , formal-property-verification , Assertion-property	1	757	February 21, 2022
What is unnamed uvm_root type? UVM UVM , systemverilog-uvm	1	701	February 21, 2022
RAL model UVM UVM , Cookbook-RegistersSpecification	1	552	February 21, 2022
UVM prints not printing time value after decimal point UVM UVM	6	1866	February 21, 2022
Comparison of class handles SystemVerilog SystemVerilog	2	1279	February 21, 2022
Fatal_error in Driver Run_phase UVM UVM	1	458	February 20, 2022
Randomization failed for AXI burst transfer SystemVerilog SystemVerilog , constraint-randomization	1	729	February 20, 2022