// ** Fatal: (SIGSEGV) Bad handle or reference.
Time: 0 ns Iteration: 49 Process: /uvm_pkg::uvm_task_phase::execute/fork#137(#ublk#215181159#137)_7fefec2e37d File: /cadtools/mentor/Questa_10.6b/questasim/linux_x86_64/../verilog_src/uvm-1.1d/src/base/uvm_common_phases.svh
Fatal error in Task or_top_sv_unit/or_driver::run_phase at ../sv//or_driver.sv line 52
`ifndef or_driver
`define or_driver
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"or_transaction.sv"
`include"or_if.sv"
`include"or_config.sv"
class or_driver extends uvm_driver#(or_transaction);
`uvm_component_utils(or_driver)
virtual or_if.DRV vif;
or_transaction data_sent;
or_config cfg;
extern function new(string name="or_driver",uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern function void connect_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
endclass
//===========NEW CONSTRUCT=======//
function or_driver::new(string name="or_driver", uvm_component parent);
super.new(name,parent);
endfunction
//==========BUILD PHASE=======//
function void or_driver::build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(or_config)::get(this,"","or_config",cfg))
`uvm_fatal("or_driver_FATAL_ERROR","config can`t get have you set it ?????")
endfunction
//==========CONNECT PHASE=========//
function void or_driver::connect_phase(uvm_phase phase);
vif = cfg.vif;
endfunction
//=============RUN PHASE===========//
task or_driver ::run_phase(uvm_phase phase);
forever
begin
vif.a <= data_sent.a; // line no 52
vif.b <= data_sent.b;
end
endtask
`endif
//====================Environment code //==================
`ifndef or_env
`define or_env
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"or_agent.sv"
`include"or_scb.sv"
`include"or_config.sv"
`include"env_config.sv"
class or_env extends uvm_env;
`uvm_component_utils(or_env)
or_agent agt;
or_scb scb;
or_config cfg;
env_config ecfg;
extern function new(string name="or_env", uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern function void connect_phase(uvm_phase phase);
endclass
function or_env::new(string name="or_env", uvm_component parent);
super.new(name,parent);
endfunction
function void or_env::build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(env_config)::get(this , "" , "env_config" , ecfg))
`uvm_fatal("FATA_ERROR_ENVIRONMENT" , "cant get env config have you set it??")
cfg = ecfg.cfg;
if(ecfg.or_agent)
begin
uvm_config_db#(or_config)::set(this , "*" , "or_config" , cfg);
agt = or_agent::type_id::create("agt" , this);
end
//=======================SCOREBOARD=====================//
if(ecfg.or_scb)
begin
scb = or_scb::type_id::create("scb" , this);
end
endfunction
//==========================connect phase======================//
function void or_env::connect_phase(uvm_phase phase);
if(ecfg.or_scb)
begin
agt.mon.monport.connect(scb.fifo.analysis_export);
end
endfunction
`endif
//=============================test_code ==========================//
`ifndef or_test
`define or_test
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"env_config.sv"
`include"or_env.sv"
`include"or_config.sv"
`include"or_sequence.sv"
class or_test extends uvm_test;
`uvm_component_utils(or_test)
or_env envh;
or_config cfg;
env_config ecfg;
extern function new(string name="or_test",uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern function void or_configure();
extern function void end_of_elaboration_phase(uvm_phase phase);
endclass
function or_test::new(string name="or_test",uvm_component parent);
super.new(name,parent);
endfunction
function void or_test::or_configure();
//===================WRITE PART================//
if(ecfg.or_agent==1)
begin
cfg=or_config::type_id::create("cfg");
if(!uvm_config_db#(virtual or_if)::get(this,"","vif",cfg.vif))
`uvm_error(get_type_name(),"can't get have you set it????")
if (ecfg.active)
cfg.is_active=UVM_ACTIVE;
else
cfg.is_active=UVM_PASSIVE;
end
endfunction
//================BUILD_PHASE====================//
function void or_test:: build_phase(uvm_phase phase);
super.build_phase(phase);
ecfg=env_config::type_id::create("ecfg");
or_configure();
ecfg.cfg = cfg;
//cfg = ecfg.cfg;
uvm_config_db#(env_config)::set(this,"*","env_config",ecfg);
envh= or_env::type_id::create("envh" , this);
endfunction
//=====================end of elaboration phase==============//
function void or_test::end_of_elaboration_phase(uvm_phase phase);
super.end_of_elaboration_phase(phase);
uvm_top.print_topology();
endfunction
//============================TEST1=======================================//
class or_test1 extends or_test;
`uvm_component_utils(or_test1)
or_sequence1 or_seq1;
extern function new(string name="or_test1",uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
endclass
function or_test1::new(string name="or_test1",uvm_component parent);
super.new(name,parent);
endfunction
function void or_test1::build_phase(uvm_phase phase);
super.build_phase(phase);
endfunction
//=================RUN_PHAS===========================//
task or_test1::run_phase(uvm_phase phase);
phase.raise_objection(this);
or_seq1 = or_sequence1::type_id::create("or_seq1");
or_seq1.start(envh.agt.sqr);
phase.drop_objection(this);
endtask
`endif
//=======================Top module ====================//
`ifndef or_top
`define or_top
import uvm_pkg::*;
`include"uvm_macros.svh"
`include"or_test.sv"
`include"or_if.sv"
`include"or_gate.v"
module or_top();
or_if inf();
// DUT instansiate =====================//
or_gate DUT ( .a(inf.a) , .b(inf.b) , .y(inf.y) );
initial
begin
uvm_config_db#(virtual or_if)::set(null,"*", "vif", inf);
run_test("or_test1");
end
endmodule
`endif