Parameterized function/task

function algorithm is same.
but just input return data type different.
I want to parameterizd the function.
May someone give me a demo to show how to parameterized


function bit[5:0] a0(input bit[9:0] data);
 bit[5:0] dout; 
 dout = data>>4;  //just a simple example
return dout;
endfunction

function bit[15:0] a1(input bit[19:0] data);
 bit[15:0] dout; 
 dout = data>>4;
return dout;
endfunction

In reply to designer007:
I think this maybe helpful

https://verificationacademy.com/forums/systemverilog/it-possible-write-function-templates-systemverilog#reply-53631

Also the 1800-2017 LRM section 13.8 Parameterized tasks and functions has examples.

HTH,
-R