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  • Is it possible to write Function Templates in SystemVerilog

Is it possible to write Function Templates in SystemVerilog

SystemVerilog 6318
systemverilog 33
rgarcia07
rgarcia07
Full Access
218 posts
April 12, 2016 at 5:55 am

Hello,

Is it possible to write a function templates in SystemVerilog? I think in C++ you can do something like this

template 
inline T const& Max (T const& a, T const& b) 
{ 
    return a < b ? b:a; 
}

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dave_59
dave_59
Forum Moderator
10661 posts
April 12, 2016 at 9:41 am

In reply to rgarcia07:

Yes, there are two ways you can do this

By wrapping the function in a class.

class relations #(type T);
static function T Max(T a,b); 
   return a < b ? b:a;
endfunction
static function T Min(T a,b); 
   return a < b ? a:b;
endfunction
endclass

By using the let construct

let Max(a,b) = a < b ? b:a;

— Dave Rich, Verification Architect, Siemens EDA

rgarcia07
rgarcia07
Full Access
218 posts
April 12, 2016 at 5:22 pm

In reply to dave_59:

Thank you very much Dave, I was not aware of the let construct!

prashant.kaushik
prashant.kaushik
Full Access
38 posts
April 12, 2016 at 9:02 pm

In reply to dave_59:

In class 'relation', functions could be static / automatic. But it is defined as static, what is a reason for it.

pkaushik

dave_59
dave_59
Forum Moderator
10661 posts
April 12, 2016 at 9:22 pm

In reply to prashant.kaushik:

The function have a static qualifier because there is no need to construct the relations class.

Don't confuse the static class method qualifier with the a static lifetime. See https://verificationacademy.com/forums/systemverilog/automatic-variables-inside-static-method#reply-42858

— Dave Rich, Verification Architect, Siemens EDA

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