What is the usage of &&& operator in system verilog?

SystemVerilog
1

Application of the &&& operator

2

In reply to Nitin C J:

The &&& operator has 2 distinct applications.

In a timing check, it is a qualification of event

@(posedge A && B) means the result of A && B goes from 0 to 1.
@(posedge A &&& B) means A goes from 0 to 1 AND B ia 1.

SystemVerilog added the iff keyword, so this is now equivalent to

@(posedge A iff B) means A goes from 0 to 1 AND B ia 1.

When using tagged unions, the &&& operator is part of a pattern matching condition

module top;
  
typedef union tagged {
   void Invalid;
   real Simple;
   struct {
     real Re;
     real Im;
   } Complex; 
} Vint;
  
  Vint Number;
  
  initial begin
    Number = tagged Simple 1.0;
    $display("%p",Number);
    Number = tagged Complex '{1.0, 0.0};
    $display("%p",Number);
    if (Number matches (tagged Complex '{.Re,.Im}) &&& Im == 0.0)
      $display("Imaginary part is 0");
  end
endmodule