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assume following conditions:
sim starts at t=0ns;
at t=3ns: sig_a changes 0->1 and clk_1 is also turned off right after the posedge (half of clk_1 was visible to check i.e. the posedge :: check image attached)
at t=7ns: the clocks are turned back on and by that time the sig_b which was correctly 0 at the the time of change now comes back to 1, since assertion will be triggered at this point i.e. t=7ns the check is bound to fail in such scenario.
How can we modify the check so that it handles such sampling clks turning of scenarios gracefully?
In reply to ViVer:
I don’t understand the issue.
($change(sig_a) |-> sig_b==0); says that when the sampled value of sig_a changes, then IN THE SAME CYCLE the sampled value of sign_b equals 0.
Your diagram "triggers @7ns, fails @8ns seems to indicate an assertion like:
($change(sig_a) |-> ##1 sig_b==0);
The fact that the clock turns off has nothing to do with this.
I don’t understand the issue, but maybe this is what you want:
property check_sigs;
@(posedge clk_1) disable iff (disable_check)
($change(sig_a) |-> @(negedge clk_1) sig_b==0);
// Checking the sig_b 0.5ns after the psoedge of clk_1.
endproperty
I don’t follow what you are asking. sig_a only changes at time 3ns and at no other time according to your diagram. Can you create an example stimulus that shows the when you expect the assertion passing and then failing.
So at 3ns the assertion will sample the sig_a value to be 0 (in prepone region-just before the clock edge) and when the clocks return at 7ns the assertion will sample the value to be 1. This will be considered as a 0->1 change and check will be triggered. Is there any way where we can say like the last signal change was before the sampling clk gap so don’t consider it.
I thought something like this:
• Keepping a var that remembers the time of the last falling edge of the clock.
• Keeping a var that remembers the time of the last transition of the sig_a.
• Keeping a var sig_a_last signal that remembers what the sig_a was before the previous clock edge.
• At the rising edge of the clock, if sig_a!=sig_a_last, throw an assertion if the sig_a transition occurred outside the range of the last falling edge of the clock and the current time.
but I am not able to put/employ it in code exactly.
I am NOT planning om a new edition of my 4th edition of my SVA nook.
What I have been doing is writing papers that supplement useful info and approaches in using SVA. Below is a link to the list of papers and books that I wrote, many now donated.
