In reply to ViVer:
I don’t understand the issue.
($change(sig_a) |-> sig_b==0); says that when the sampled value of sig_a changes, then IN THE SAME CYCLE the sampled value of sign_b equals 0.
Your diagram "triggers @7ns, fails @8ns seems to indicate an assertion like:
($change(sig_a) |-> ##1 sig_b==0);
The fact that the clock turns off has nothing to do with this.
I don’t understand the issue, but maybe this is what you want:
property check_sigs;
@(posedge clk_1) disable iff (disable_check)
($change(sig_a) |-> @(negedge clk_1) sig_b==0);
// Checking the sig_b 0.5ns after the psoedge of clk_1.
endproperty
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…
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Reflections on Users’ Experiences with SVA, part 2
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Understanding and Using Immediate Assertions
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SUPPORT LOGIC AND THE ALWAYS PROPERTY
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SVA Alternative for Complex Assertions
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SVA in a UVM Class-based Environment
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SVA for statistical analysis of a weighted work-conserving prioritized round-robin arbiter.
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