How to write SVA when the antecedent is changing at the same time when the sampling clock is getting off?

SystemVerilog
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7

In reply to ben@SystemVerilog.us:

In reply to ViVer:


property check_sigs;
@(posedge clk_1) disable iff (disable_check)
($change(sig_a) |-> $past(sig_b)==0);
endprope

This will work, thanks a lot for the help.
@ben are you planning to release any new edition for your book anytime soon, I am planning to purchase it.