Verification Academy

Topic	Replies	Views	Activity
Multiple sequencers with single driver UVM UVM , UVM-Driver , REQ-FIFO	2	724	June 4, 2023
Using Ternary operator in SVA for Temporal scenario SystemVerilog SystemVerilog , Using-Ternary-operator-in-SVA-for-Temporal-scenario	6	952	June 4, 2023
How to know on which sequence the current sequencer is running? UVM UVM	2	500	June 3, 2023
Can we use assert to check a property and still mask the "offending" message that gets reported if the assertion fails SystemVerilog SystemVerilog , SVA-Assertion , SVA-Property	1	480	June 2, 2023
Cast parameterizable class whose parameter is extended from the other UVM UVM , uvm-parameter-polymorphism	1	330	June 2, 2023
Basic mod function with negative integer - strange result SystemVerilog SystemVerilog	3	503	June 2, 2023
Systemverilog shift operator question SystemVerilog SystemVerilog , System-Verilog , shift-operater	8	1518	June 2, 2023
Function overloading in SV - workaround? SystemVerilog SystemVerilog	0	357	June 2, 2023
SVA - To check value at previous OR current OR next clock cycle SystemVerilog SystemVerilog , System-Verilog , SVA-Assertion-Systemverilog	6	1336	June 2, 2023
Uvm1.2 "starting_phase = null" but sequence still working UVM UVM , starting_phase	2	454	June 2, 2023
Will always_comb block trigger if the signal value changes from 0/1 to X SystemVerilog SystemVerilog , System-Verilog , always_comb , force-release	6	1045	June 1, 2023
How to access a variable inside a UVM class and connect it to an SV interface? UVM UVM , Class-variables-inside-SV-Interface	1	371	June 1, 2023
Why p sequencer UVM UVM	5	6591	June 1, 2023
Bind keyword in multiple instances SystemVerilog SystemVerilog	1	727	June 1, 2023
Coverage for the value difference between associative arrays SystemVerilog SystemVerilog , Coverage , System-Verilog , associative_arrays	1	388	June 1, 2023
About UVM in order Comparator class UVM UVM , convert , comparator , compare , UVM-IN-ORDER-COMPARATOR	1	366	June 1, 2023
UVM UVM SystemVerilog , UVM , -UVM-warnings-disable	1	384	June 1, 2023
Using Set_inst_override_by_type() override uvm_object UVM UVM , uvm-uvm_config_db , environment , set_inst_override_by_type	1	438	June 1, 2023
System verilog Assertion fail SystemVerilog SystemVerilog , assertion , SVA-PAST-multiple-clock-domain	1	589	June 1, 2023
Function to return a struct with an unconstrained field SystemVerilog SystemVerilog , unconstrained	3	699	May 31, 2023
Modeling for clock , request & ack handshake SystemVerilog SystemVerilog	3	463	May 31, 2023
Can interface be instantiated in array? SystemVerilog SystemVerilog	1	452	May 31, 2023
Performance comparison between $system and DPI SystemVerilog SystemVerilog	3	594	May 31, 2023
Running/Ending Directed Test Preloaded Into CPU Memory? UVM UVM	10	869	May 30, 2023
Assume for formal verification SystemVerilog SystemVerilog , assertion , Formal-Verification , system-verilog-assertions-disable-iff	4	890	May 30, 2023
System Verilog Datatypes SystemVerilog SystemVerilog	1	359	May 30, 2023
Chat.openai experience for a funky counter in SV with SVA SystemVerilog SystemVerilog	0	356	May 30, 2023
Using and / or operator within Multi -clocked Sequence SystemVerilog SystemVerilog , Using-and--or-operator-within-Multi-clocked-Sequence	9	1576	May 28, 2023
Variable type is not user defined type UVM UVM , mixed-UVM-OVM , User-defined-variable , Systemverilog-UVM-RAL , uvm-compilation	4	1113	May 27, 2023
Hi, could you please provide simple SPI protocol testbench code in UVM? UVM UVM , uvm-testbench-components , uvm-design	1	478	May 26, 2023