Verification Academy

Topic	Replies	Views	Activity
Associative array handle copy, coherency issue UVM UVM , associative_arrays , array_handle	1	577	August 10, 2022
How to use $system with substitutions SV/UVM SystemVerilog SystemVerilog , system , Macro-and-Argument-Substitution-Via-Macro , Text-Substitution-Query	1	493	August 10, 2022
Array and printing the varible SystemVerilog SystemVerilog , uvm-print	2	495	August 10, 2022
Implementing driver with configurable number of outstanding transactions UVM UVM	0	540	August 9, 2022
What is the memory structure for a systemverilog queue SystemVerilog SystemVerilog , System-Verilog , queues-systemverilog	4	971	August 9, 2022
Avoiding non-user defined bins within cross SystemVerilog SystemVerilog , Avoiding-non-user-defined-bins-within-cross	2	752	August 9, 2022
Mirror value is not getting updated after read/write using reg model UVM UVM , mirror-value , RAL-UVM-PREDICTOR	0	376	August 9, 2022
Array reduction sum method with clause overflow protection SystemVerilog SystemVerilog	6	835	August 8, 2022
Remote Monitoring and control of Home appliances from cloud using EDGE Artix 7 FPGA board SystemVerilog SystemVerilog	1	414	August 8, 2022
Checker to check whether given address is of 64 bit SystemVerilog SystemVerilog , checker , 64-bit	1	510	August 8, 2022
Regarding to SystemVerilog Environment SystemVerilog SystemVerilog	1	482	August 8, 2022
Fork join SystemVerilog SystemVerilog	3	688	August 7, 2022
How to find and select from multiple drivers to same variable using assertions SystemVerilog SystemVerilog , assertion	4	885	August 7, 2022
How to execute a recursive factory override? UVM UVM , uvm-factory	2	688	August 6, 2022
Function with timing control SystemVerilog SystemVerilog	4	1679	August 5, 2022
How to pass a variable into a Bit-Width SystemVerilog SystemVerilog , bit-width , bit-slicing	1	1048	August 5, 2022
Randomization of array of basic type, vs randomization of array of structs SystemVerilog SystemVerilog , constraint-randomization	4	909	August 5, 2022
System Verilog Strings SystemVerilog SystemVerilog , systemverilog-Strings	1	616	August 5, 2022
A way to write constraint which allocates active channels to ports SystemVerilog SystemVerilog , stimuli	6	993	August 4, 2022
$value$plusargs is not working UVM UVM	1	408	August 4, 2022
Can I put an assert statement inside of a task? SystemVerilog SystemVerilog	6	2213	August 3, 2022
Execution of build_phase is not happening for multiple instances of same uvm_env in base_test UVM UVM , build_phase-execution-failed	2	473	August 3, 2022
Regarding default bins SystemVerilog SystemVerilog , Regarding-default-bins	1	491	August 3, 2022
Ask a question about class structure (base/child) SystemVerilog SystemVerilog	4	568	August 3, 2022
$monitor does not get printed SystemVerilog SystemVerilog , printstatements	6	994	August 2, 2022
$displayh SystemVerilog SystemVerilog , System-Verilog , systemverilog-Arrays-packedarrays-unpackedarrays	1	865	August 2, 2022
Order of function call via Constraint V/S with covergroup expression Coverage Coverage , Order-of-function-call-via-Constraint-VS-with-covergroup-expression	3	821	August 2, 2022
UVM call back on sequence UVM UVM , UVM-callback	1	454	August 2, 2022
Clock generator task - forever statement makes the simulator hang SystemVerilog SystemVerilog	9	1959	August 2, 2022
Execution interrupted or reached maximum runtime UVM UVM , EDA-Playground , Debug , execution-in-uvm , UART-VIP	1	505	August 1, 2022