How to pass a variable into a Bit-Width

SystemVerilog
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1

I have a code that is something like this –

logic [6:0] mask = 7'b001_1011; 
logic [31:0] masked_number;
function void masks ();
  masked_number[31: (32-mask)] = 'd1;
  masked_number[32-mask-1):0] = 'd1;
endfunction

This gives me an error as below –
What is the right way to code this
Error-[IRIPS] Illegal range in part select
…/…/<file_name>, 221
The range of the part select is illegal:
Unknown range in part select.this.masked_number[31:(32 - this.mask)]

Error-[IRIPS] Illegal range in part select
…/…/<file_name>, 222
The range of the part select is illegal:
this.masked_number[((32 - this.mask) - 1):0]

2

In reply to Anand Sharma:

Verilog/SystemVerilog requires all integral operands to have fixed sized widths at compilation.

To work around this, you can use a combination of shifts and masks.

function void masks ();
  int position;
  logic [31:0] upper,lower;
  position = 32-mask;
  upper = 'd1;
  lower = 'd1;
  masked_number = upper << position | (32'd2**position)-1 & lower;
endfunction