Checker to check whether given address is of 64 bit

SystemVerilog
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1

Hi,

i would like to write a checker which should check whether the given address is of 64 bit?

can anyone help or give idea how to write the checker to check particular variable is of 64 bit.

2

In reply to abhi.khati7274:

You need to be more descriptive. By “given address is of 64 bit”, do you mean a signal holding a value representing an address can hold up to 64 bits? Or do you mean something else?

($bits(signal) == 64) is true if the width of the signal is 64-bits