Verification Academy

Topic	Replies	Views	Activity
Expanding Macros SystemVerilog SystemVerilog	3	598	September 26, 2022
Error : formal and actual do not have assignment compatible data types (expecting datatype compatible with 'class uvm_pkg::uvm_component' but found 'packed array' instead) UVM UVM	1	1186	September 26, 2022
How to write a checker for req/ack without using assertion SystemVerilog SystemVerilog	1	751	September 26, 2022
What is the difference wire and logic? SystemVerilog SystemVerilog , SystemVerilog-modport	1	1203	September 25, 2022
Constraints to generate 10 continuous bits as 0 and remaining as 1 SystemVerilog SystemVerilog , System-Verilog , constraint-randomization	1	1085	September 24, 2022
Extend a uvm_component whose member is another inherited uvm_component class UVM UVM , Multiple-class-inheritance	5	1312	September 23, 2022
Uvm_do macro UVM UVM , uvm_do-pre_body , post_body	2	438	September 23, 2022
User - defined frontdoor V/S UVM_FRONTDOOR UVM UVM , User-defined-frontdoor-VS-UVM_FRONTDOOR	1	677	September 22, 2022
How SV Macro get processed? SystemVerilog SystemVerilog , SV-Macro	2	929	September 22, 2022
UVM configuration NULL pointer dereference Problem UVM UVM , uvm-uvm_config_db	11	1497	September 22, 2022
How to pass items between 2 sequences in a virtual sequence without involving uvm_confib_db UVM UVM	1	417	September 22, 2022
Extern "C" in C and C++ SystemVerilog SystemVerilog , dpi-c	3	901	September 22, 2022
How to read formatted data from a file (with example)? SystemVerilog SystemVerilog , read-formatted-data	6	6085	September 22, 2022
GETTING ERROR WITH THE DISPLAY STATEMENT SystemVerilog SystemVerilog , error , System-Verilog , display-error , help	1	1246	September 21, 2022
Array randomization SystemVerilog SystemVerilog	7	1950	September 21, 2022
Driver lost the first cycle of data SystemVerilog SystemVerilog , driver-systemverilog	1	294	September 21, 2022
Bad pointer access... while opening waveform SystemVerilog SystemVerilog , System-Verilog , waveform , vsim , bad-pointer-access , closing-vish	1	788	September 21, 2022
UVMF: virtual interface and and hierarchical references UVM UVM , UVMF	1	685	September 20, 2022
Re-lock RAL model UVM UVM , uvm-ral	0	536	September 20, 2022
Print problem UVM UVM	2	451	September 20, 2022
How to end simulation when there are forever-loops in sequence and monitor? UVM UVM , systemverilog-uvm , forever	4	1819	September 19, 2022
Multiple driving interfaces to multiple register models UVM UVM	0	311	September 18, 2022
Circular shift constraint SystemVerilog SystemVerilog , System-Verilog , constraint-randomization	3	1214	September 18, 2022
Deciding REQ and RSP type parameters for Driver , Sequence and Sequencer in RAL UVM UVM , Deciding-REQ-and-RSP-type-parameters-for-Driver , Sequence-and-Sequencer-in-RAL-	0	441	September 17, 2022
Using uvm_transaction :: end_event for Sequence - Driver Communication UVM UVM , Using-uvm_transaction-end_event-for-Sequence-Driver-Communication	0	492	September 17, 2022
Assertion Disabling for specific time and reenable it SystemVerilog SystemVerilog , assertion , disable-assertion	4	1612	September 16, 2022
Scoreboard with multiple input streams UVM UVM	3	1215	September 16, 2022
UVM do_copy virtual method SystemVerilog SystemVerilog , System-Verilog , do_copy-uvm_sequence_item , base_test-uvm_tlm_fifo	2	713	September 16, 2022
Sliding_0 Pattern SystemVerilog SystemVerilog , Sliding-Patterns , Sliding_0 , Sliding_1 , Sliding-Pattern	1	471	September 15, 2022
SVA - Repeat pattern until_with SystemVerilog SystemVerilog	3	1196	September 15, 2022