Sliding_0 Pattern

SystemVerilog
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1

I am trying to develop one sliding_0 sequence, but I am not sure why it is not working. My approach is as follows -
1111 1110 ==> FE
1111 1101 ==> FD (-1) (hex - 2^0)
1111 1011 ==> FB (-2) (hex - 2^1)
1111 0111 ==> F7 (-4) (hex -2^2)
1110 1111 ==> EF (-8) (hex - 2^3)
1101 1111 ==> DF (-16 or -10H) (hex - 2^4)
1011 1111 ==> BF (-32 or -20H) (hex - 2^5)
0111 1111 ==> 7F (-64 or -40H) (hex -2^6),

the code that I have written is -

module sliding();
  bit [7:0] count_value = 8'hFE;

task sliding_0;
  for(int i=0; i<7; i++)begin
    count_value [i] = (count_value - (2^i));
    $display("count value is %d", count_value);
end
endtask
endmodule
2

In Verilog, ^ is the XOR operator. You should use ** instead. Also, you should subtract the whole value, not just assign a specific bit using [i]:

module sliding();
  bit [7:0] count_value = 8'hFE;

  initial sliding_0();

  task sliding_0;
    for(int i=0; i<7; i++)begin
      count_value -= 2**i;
      $display("count value is %d 'b%b 'h%x",count_value,count_value,count_value);
    end
  endtask
endmodule

This prints:

count value is 253 'b11111101 'hfd
count value is 251 'b11111011 'hfb
count value is 247 'b11110111 'hf7
count value is 239 'b11101111 'hef
count value is 223 'b11011111 'hdf
count value is 191 'b10111111 'hbf
count value is 127 'b01111111 'h7f