How to end simulation when there are forever-loops in sequence and monitor?

UVM
, ,
1

Dear All,

I’m trying to understand uvm phase process. Especially, we can implement forever statment such as the below example.

class my_monitor extends uvm_monitor;
 `uvm_component_utils (my_monitor)
...
 function new (string name, uvm_component parent)
 super.new (name, parent);
 endfunction

 virtual function void build_phase (uvm_phase phase)
 super.build_phase (phase);
 endfunction

 virtual task run_phase (uvm_phase phase);

 forever begin
 ...
 data_obj.data = vif.data;
 data_obj.addr = vif.addr;
...
 if (enable_coverage)
 data_obj.cg_trans.sample();
 // Send data object through the analysis
 mon_analysis_port.write (data_obj);
 end
 endtask
...
endclass

As you can see the above, there is implemented with foreever statement.
I’m wonder that if we use forever statment, who/how does kill it?
In UVM Monitor - Verification Guide , some article answered by “don’t use forever statments”.
Even if I implement a raise/drop objection in run_phase, doesn’t forever stop?

2

In reply to UVM_LOVE:

The advice “don’t use forever statements” is incorrect. All run_phase tasks in all components get killed when the last objection drops. You would not put a raise/drop objection around a forever loop like those used in a monitor or driver unless there was some condition to break out of the forever loop.

3

In reply to dave_59:

The statement “don’t use forever statements” is related to the body task of sequences. If your sequence runs forever your simulation will never stop.

4

In reply to chr_sue:

Incorrect.All run_phase tasks in all components get killed when the last objection drops. A slave/responder sequence is good counter argument.

5

In reply to dave_59:

Hi in case of response handler Sequance (responder Sequance) which needs to have under forever loop. what do you suggest to achieve end of simulation independent of this Sequance completion.??