UVM do_copy virtual method

SystemVerilog
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1

In the do_copy virtual method, we pass the argument to super using super.do_copy(rhs). What is the reason for that?

class stimulus extends uvm_sequence_item;
rand int address;
`uvm_object_utils(stimulus)
virtual function void do_copy(uvm_object rhs);
stimulus rhs_;
super.do_copy(rhs);   // Is it necessary ?
$cast(rhs_,rhs);
address = rhs_.address;
endfunction
function new(string name = "stimulus");
super.new(name);
endfunction
endclass
2

Yes it is required. This is how OOP is expected to work.

Assume the parent class has two variables “a and b”, and the child class has an extra variable “c”. This do_copy method first calls the parents do_copy method (i.e, super.do_copy) so that it may copy a and b variables from rhs.a and rhs.b. After it is done the current do_copy method will copy “C” from rhs.c

3

In reply to logie:

Thanks for the reply. In this case, it is not required. Because uvm_sequence_item is having no property; it’s a base class. But in such a situation where we have called a class (stimulus2) that is the grandchild of uvm_sequence_item and its (stimulus2) parent class (stimulus1) is having some extra properties, we need to call super.do_copy. Did I get this correct?

 I have one more doubt and it's regarding SV and UVM testbench. In SV, we generally import pkg inside the test file and we include the test file in the top module. On the other side, in UVM we include the test file along with other component and object files inside pkg and we import that pkg into the top module. Is it necessary to follow this flow?
  1. In SV, can we not add the test file to pkg and that pkg gets imported to the top module?
  2. In UVM, can we not add the test file to the top file and import pkg to the test file?