Verification Academy

Topic	Replies	Views	Activity
Uvm_info without printing the file name and other details UVM UVM	2	2745	October 9, 2022
Define+macro in tool compilation vs define Macro in SV SystemVerilog SystemVerilog , definemacro	3	1381	October 7, 2022
Assertion signal high between two triggers SystemVerilog SystemVerilog	1	602	October 7, 2022
Hi all I have a question regarding driving sequence items in a certain way. The details are provided below. Please let me know if I am doing anything wrong with my code UVM UVM , System-Verilog , fork_join , UVM-DRIVER-INTERFACE	1	590	October 7, 2022
In the TLM, Why we need a export UVM UVM , UVM-TLM-Port_Export	2	869	October 7, 2022
Backdoor HDL Path UVM UVM , Backdoor-HDL-Path	0	501	October 6, 2022
Assumption for req and ack and response interface SystemVerilog SystemVerilog , assertion , assumption	1	1132	October 6, 2022
Fork join with hang process UVM UVM	3	607	October 6, 2022
Formal Verification SVA assume signal to NOT toggle at negedge SystemVerilog SystemVerilog , Formal-Verification , assume-sva	9	1775	October 6, 2022
Associative Array Confusion - arr[int] vs arr[*] SystemVerilog SystemVerilog , Assoc-array-key--vs-int	1	352	October 5, 2022
Is there a way I can disable checking for a specific register in a register map defined using uvm_reg? UVM UVM , uvm_reg_map , uvm_reg	2	1655	October 5, 2022
Automatic variable SystemVerilog SystemVerilog	5	7472	October 4, 2022
System Verilog Assertions: Difference between ##1 and \|=> SystemVerilog SystemVerilog , assertion	2	1416	October 4, 2022
Array with random numbers from 0 to Size-1 (Without duplicates) SystemVerilog SystemVerilog , constraint-randomization , system-verilog-constraints	3	1101	October 3, 2022
Queue problem SystemVerilog SystemVerilog	1	450	October 3, 2022
Question related to array SystemVerilog SystemVerilog	1	402	October 2, 2022
Can we set option.goal and option.weight for a coverpoint from top or env or test Coverage Coverage , coverage-optiongoal-optionweight-goal-weight	1	492	October 1, 2022
Getting an error name : Expecting the keyword 'endclass' UVM UVM , Compilation-Error	1	1065	October 1, 2022
How to add leading zeros to a transaction print? UVM UVM	4	1197	September 30, 2022
How to disable RAL registers creation from env UVM UVM , UVM-UVMRAL	4	750	September 30, 2022
How to hit a cross point of two iff guarded coverpoint Coverage Coverage , cross-coverage	2	672	September 30, 2022
Task calling in sequence /Test UVM UVM	4	564	September 29, 2022
Define vs. parameter - difference SystemVerilog SystemVerilog	4	8825	September 29, 2022
Rsort() for Multidimensional Array SystemVerilog SystemVerilog , rsort-for-Multidimensional-Array	8	1041	September 29, 2022
UVM ral backdoor read can only get the value of current cycle UVM UVM	1	311	September 28, 2022
Can we call child class in parent class UVM UVM	4	1239	September 28, 2022
Proper use of while(1) inside fork/join , when while(1) is in initial block and module also has final block SystemVerilog SystemVerilog	3	1271	September 27, 2022
Connection switching - Runtime UVM UVM , Driver-sequencer-Handshake , Handshaking , CONNECT-PHASE , UVM-DRIVER-INTERFACE	3	755	September 27, 2022
Module based coverage vs class based coverage Coverage Coverage , coverage-UVM-module-class	1	1056	September 26, 2022
Can only bind to modules or module instances SystemVerilog SystemVerilog , bind , system-verilog-coverage-with-clause-coverpoints	3	2634	September 26, 2022