Can we call child class in parent class

UVM
1

Hi

is there any method where i can call child class in runphase of parent class.

To add more pointer:
I’ll have to call childclass testcase in runphase of parentclass to check an error scenario

How do i proceed?

2

In reply to Swetha_ch:

It would help to show an example because parent and child classes are ambiguous terms in UVM. Classes derived from uvm_component (like uvm_test) have parent-child relationships, but many people incorrectly use the same words for inheritance when they really mean base and extened classes.

If you really mean inheritance, virtual methods are used to call extended routines from the base class.

class base_test extends uvm_test;

  virtual task run_phase(uvm_phase phase);
    ...
    check_errors();
    ...
  endtask
  virtual function void check_errors();
    // empty
  endfunction
endclass
class extended_test extends base_test;
  virtual function void check_errors();
    ///what you need to check
  endfunction
endclass
1 Like
3

In reply to dave_59:

In reply to Swetha_ch:
It would help to show an example because parent and child classes are ambiguous terms in UVM. Classes derived from uvm_component (like uvm_test) have parent-child relationships, but many people incorrectly use the same words for inheritance when they really mean base and extened classes.
If you really mean inheritance, virtual methods are used to call extended routines from the base class.

class base_test extends uvm_test;
virtual task run_phase(uvm_phase phase);
...
check_errors();
...
endtask
virtual function void check_errors();
// empty
endfunction
endclass
class extended_test extends base_test;
virtual function void check_errors();
///what you need to check
endfunction
endclass

Here my case is, base test is extending from uvm_test and my testcase (for eg:x) is extending from base test. Now i’ll have to use x in the run_phase task of base test.

4

In reply to dave_59:

In reply to Swetha_ch:
It would help to show an example because parent and child classes are ambiguous terms in UVM. Classes derived from uvm_component (like uvm_test) have parent-child relationships, but many people incorrectly use the same words for inheritance when they really mean base and extened classes.

Hi Dave,

I’ve recently stumbled upon a stackoverflow question where you mentioned that he/she is mixing up the terms parent and child with class inheritance. I couldn’t understand your explanation over there, and here as well… How I understand the concept of inheritance is that a class (child class) can extend another class (parent class) by inheriting its features. In this example, base_test is a child of the parent uvm_test, and the child base_test inherits whatever virtual functions or tasks or fields there are from the parent uvm_test. In Specman which I’ve had experience for only a few years, “inheritance” is also applied to a child unit or struct that “extends” the parent unit or struct via the constructs like or when.

5

In reply to renvillph:

The problem is when parent/child terminology is used to describe different kinds of class relationships. There is a difference between the relationship of a base class type and its extended types, versus the relationship of class objects in a tree data-structure (like what uvm_component creates). If you just say “parent class” by itself as in the original question here, we don’t know if they are referring to a “base class type”, or a component class object at a level above the current object.

This problem may be more prominent in UVM because of the parent/child object relationships used by the test/env/agent/driver/monitor component hierarchy. But I’ve also seen people get confused with inheritance when constructing an extended object called a “child” and thinking they have created two objects, both a parent and a child.

Another recent explanation:
https://verificationacademy.com/forums/uvm/extend-uvmcomponent-whose-member-another-inherited-uvmcomponent-class#reply-108834