Can only bind to modules or module instances

SystemVerilog
, ,
1

I am reasonably new to the bind/module instantiation, would need a help here.

Error Signature:


Error-[SVA-COBMMI] Can only bind to modules or instances.
bind 
top.****some_file_csr
bind_dut bind_dut_i(.*); 




bind `DEFINE.dut_m bind_dut #(.NUM_INTF(`NUM_INTF),
                                                  ._NUM(`_NUM),
                                                  ._WIDTH(`_WIDTH),
                                                  .DUT_INSTANCE(`BIND_DUT_INST)) bind_dut_i ( .* ); 




//
I  am not sure about how are we binding to this dut_m instace // any help here would be helpful.  
some_dut /* its a module 8 */ #(.NUM_INTF (NUM_INTF),
         .DUT_INSTANCE (`BIND_DUT_INST)) dut_m

bind_dut is a module and having all 4 parameter in it.
FYI:
dut_m is having 20 port connection.
bind_dut is having 18 port connection

2

In reply to m_r_m:

The error message you show has identifiers that do not match the code you show.

3

In reply to dave_59:

Updated, thanks

4

In reply to m_r_m:

What are your macro definitions?