In the TLM, Why we need a export

UVM
,
1 
 In the TLM, Why we need a export,because I can connect a port directly to the IMP,without a export.
2

In reply to liuxiaole:

You make a direct connection when the port and imp are at the same level in the testbench hierarchy. But as you add layers to the hierarchy, you need to create exports providing access to the IMP. In TLM-speak, the port is the caller/initiator and the export/imp is the callee/responder.

3

In reply to dave_59:

Hello, Dave

Actually, a direct connection of tlm port - tlm impl. between components in different hierarchy level is working without any tlm exports.

Is it a kind of policy?

my test code is below.

A.subA.subsubA.a_p.connect(B.subB.a_impl); // direct connection


import uvm_pkg::*;
`include "uvm_macros.svh"

class my_data extends uvm_object;
  `uvm_object_utils(my_data)
  
  int id;
  
  function new(string name="my_data");
    super.new(name);
  endfunction
  
  virtual function void do_print(uvm_printer printer);
    super.do_print(printer);
    printer.print_field_int("id", id, $bits(id), UVM_DEC);
  endfunction
endclass

class subsubcomponentA extends uvm_component;
  `uvm_component_utils(subsubcomponentA)
  
  uvm_analysis_port#(my_data) a_p;
  my_data data;
  int cnt = 3;

  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction
  
  virtual function void build_phase(uvm_phase phase);
    a_p = new("a_p", this);
  endfunction
  
  virtual task run_phase(uvm_phase phase);
    `uvm_info(get_type_name(), "run_phase", UVM_LOW)
    
    while(cnt>0) begin
      `uvm_info(get_type_name(), $sformatf("before a_p.write(%d)", cnt), UVM_LOW)
      data = my_data::type_id::create("data");
      data.id = cnt--;
      a_p.write( data );
    end
  endtask
endclass

class subcomponentA extends uvm_component;
  `uvm_component_utils(subcomponentA)
  
  subsubcomponentA subsubA;

  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction
  
  virtual function void build_phase(uvm_phase phase);
    subsubA = subsubcomponentA::type_id::create("subsubA", this);
  endfunction
endclass

class componentA extends uvm_component;
  `uvm_component_utils(componentA)
  
  subcomponentA subA;  
  
  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction
  
  virtual function void build_phase(uvm_phase phase);
    subA = subcomponentA::type_id::create("subA", this);
  endfunction
endclass

class subcomponentB extends uvm_component;
  `uvm_component_utils(subcomponentB)
  
  uvm_analysis_imp#(my_data, subcomponentB) a_impl;

  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction
  
  virtual function void build_phase(uvm_phase phase);
    a_impl = new("a_impl", this);
  endfunction
  
  function void write(my_data data);
    `uvm_info(get_type_name(), "write", UVM_LOW)
    data.print();
  endfunction
endclass

class componentB extends uvm_component;
  `uvm_component_utils(componentB)
  
  subcomponentB subB;  
  
  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction
  
  virtual function void build_phase(uvm_phase phase);
    subB = subcomponentB::type_id::create("subB", this);
  endfunction
endclass

class my_test extends uvm_test;
  `uvm_component_utils(my_test)
  
  componentA A;
  componentB B;
  
  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction
  
  virtual function void build_phase(uvm_phase phase);
    A = componentA::type_id::create("A", this);
    B = componentB::type_id::create("B", this);
  endfunction
  
  virtual function void connect_phase(uvm_phase phase);
    A.subA.subsubA.a_p.connect(B.subB.a_impl);
  endfunction
endclass


module tb;
  initial begin
    run_test();
  end
endmodule