Topic	Replies	Views	Activity
UVM 1.2 new warning - a resource with meta characters in the field name has been created UVM UVM , uvm_reg_block , Resource_db , UVMRSRCNOREGEX , UVM-12 , uvm-warning	12	7415	December 18, 2025
Where is the best place to put the register model? UVM uvm_reg_block , register-assistant	0	299	December 21, 2023
Is it possible to map 2 different sequencers to a reg_map one for read one for write? UVM UVM , uvm_reg_block , multiple-sequencers	18	1548	December 16, 2022
Set sub register block from the top register block to below component hierarchy UVM UVM , uvm_reg_block , uvm_reg_block-multiple-reg-blocks	2	654	March 10, 2022
Reuse constraints in child classes UVM SystemVerilog , UVM , uvm_reg_block , uvm-ral , uvm_ral	1	1078	February 15, 2021
UVM_BIG_ENDIAN - Address order when n_bytes is set to 1 UVM UVM , uvm_reg_block , uvm_reg_map , UVM_BIG_ENDIAN	0	1289	November 20, 2019
RAL: uvm_reg_map base address does not work UVM UVM , RAL , uvm_reg_block , uvm_reg_map , m_base_addr	3	2829	March 5, 2018
How the SPI reg2bus/bus2reg functionality taken care in "a complete working example uvm_spi_bl_reg_tb.tgz"? UVM UVM , uvm_reg_adapter , uvm_reg_block , reg2bus , bus2reg , Cookbook-RegistersIntegration	3	1125	December 9, 2017
Register model integration, set_inst_override_by_type UVM UVM , uvm_reg_block , set_inst_override	4	2192	May 19, 2015
Shared address maps in uvm_reg_block UVM UVM , RAL , uvm_reg_block , uvm_reg_map	1	3343	December 24, 2014
Special register(s) with fields based on a mode UVM UVM , registers , RAL , uvm-register , uvm_reg_block	0	1911	April 16, 2014
Cannot predict while reg is being accessed UVM UVM , uvm_reg_block , predict	0	1324	April 7, 2014
Register callback to uvm_reg_block model UVM UVM , UVM-callback , uvm_reg_cbs , uvm_reg_block	0	2247	March 13, 2014

uvm_reg_block