In reply to Prawin kumar:
Hi,
Why this error is occurred?
task run_phase(uvm_phase phase);
ac_lpc_tx_seq test_seq;
phase.raise_objection(this, “starting test_seq”)
test_seq = ac_lpc_tx_seq::type_id::create(“test_seq”,this);
test_seq.start(env.agent.sequencer);
#100;
phase.drop_objection(this, “finished test_seq”);
endtask: run_phase
ERROR:“Incompatible types at assignment: .test_seq<ac_lpc_tx_seq>create(”“test_seq”“,this,”“”“)<uvm_sequence_item>.”"
Thanks,
In reply to Prawin kumar:
Looks a Little bit strange, because you never mentioned ‘test_seqcreate’.
My guess is your code does not look like this:
test_seq = ac_lpc_tx_seq::type_id::create(“test_seq”,this)
In reply to chr_sue:
Hi,
That is create method right,for test_seq.for rise and drop objection for sequence.
even though am getting error
E:“Incompatible types at assignment: .test_seq<ac_lpc_tx_seq> ← create(”“test_seq”“,this,”“”“)<uvm_sequence_item>.”
In reply to Prawin kumar:
Is the sequence compatible with the sequencer? It looks like it is not. Does the sequence generate the same seq_items as the sequencer is parameterized?
In reply to Prawin kumar:
Could you please provide the code for your test_seq and the corresponding sequencer.
In reply to chr_sue:
class ac_lpc_sequencer extends uvm_sequencer#(sequence_item);
`uvm_component_utils(ac_lpc_sequencer)
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
endclass:ac_lpc_sequencer
//////////////////////////////////////////////////////////////////////
class ac_lpc_tx_seq extends uvm_sequence#(sequence_item);
sequence_item req;
function new(string name = “ac_lpc_tx_seq”);
super.new(name);
endfunction
task body;
req = sequence_item::type_id::create(“req”);
for(int i=0;i<10;i++) begin
start_item(req);
assert (req.randomize());
finish_item(req);
`uvm_info(“AC_LPC_TX_SEQ_BODY”, $sformatf(“Transmitted frame %0d”, i), UVM_LOW);
end
endtask: body
endclass:ac_lpc_tx_seq
In reply to Prawin kumar:
This looks OK.
But I found something else in the buil_phase of your env:
function void build_phase(uvm_phase phase);
env = ac_lpc_env::type_id::create("env", this);
//test_seq = ac_lpc_tx_seq::type_id::create("test_seq",this);
sequencer = ac_lpc_sequencer::type_id::create("test_seq",this); //this wrong
sequencer = ac_lpc_sequencer::type_id::create("sequencer",this); // this is correct!
if(!uvm_config_db#(virtual ac_lpc_if)::get(this, "", "vif", vif)) begin
`uvm_fatal("ac_lpc_test", "No virtual interface specified for this test instance")
end
uvm_config_db#(virtual ac_lpc_if)::set( this, "env", "vif", vif);
endfunction
In reply to chr_sue:
Hi,
Above code is wrong, because of in my ‘env’ i made the connections of scoreboard only, so no need to create ‘sequencer’ ok.
function void build_phase(uvm_phase phase);
agent = ac_lpc_agent::type_id::create(“agent”,this);
scoreboard =ac_lpc_scoreboard::type_id::create(“scoreboard”,this);
driver =ac_lpc_driver::type_id::create(“driver”,this);
monitor =ac_lpc_monitor::type_id::create(“monitor”,this);
//sequencer =ac_lpc_sequencer::type_id::create(“sequencer”,this);
if (!uvm_config_db#(virtual ac_lpc_if)::get(this, "", "vif", vif)) begin
`uvm_fatal("ac_lpc_env", "No virtual interface specified for this env instance")
end
uvm_config_db#(virtual ac_lpc_if)::set( this, "agent", "vif", vif);
endfunction
function void connect_phase(uvm_phase phase);
driver.drv_to_sb.connect(scoreboard.input_fifo.analysis_export);
monitor.item_collected_port.connect(scoreboard.output_fifo.analysis_export);
endfunction
endclass: ac_lpc_env
In reply to Prawin kumar:
Why are you creating a driver and monitor (and sequencer?) in your environment? You are creating an agent which should contain these components. In your environment, you should only create the agent and scoreboard.
In reply to cgales:
Because am made connections of driver to scoreboard and monitor to scoreboard in environment only. that’s why am creating agent components in environment also …
we cannot connect components without create right.
In reply to Prawin kumar:
The agent will create its own driver, monitor and sequencer. There is no need to create them in the environment. The agent should also have an analysis port, which is connected to the monitor’s analysis port. You will connect the agent’s analysis port to the scoreboard.
A poorly written agent won’t have an analysis port, in which case you will connect the monitor’s analysis port to the scoreboard.
In reply to cgales:
Thank you cgales
In reply to Prawin kumar:
Hi,
What is verbosity of UVM_INFO in uvm monitor.
i.e deference between UVM_LOW,UVM_HIGH,UVM_NONE,UVM_MEDIUM.
Thanks,
In reply to Prawin kumar:
This is what the Refernce Manual says:
Defines standard verbosity levels for reports.
UVM_NONE Report is always printed. Verbosity level setting can not disable it.
UVM_LOW Report is issued if configured verbosity is set to UVM_LOW or above.
UVM_MEDIUM Report is issued if configured verbosity is set to UVM_MEDIUM or above.
UVM_HIGH Report is issued if configured verbosity is set to UVM_HIGH or above.
UVM_FULL Report is issued if configured verbosity is set to UVM_FULL or above.
You should learn fo work with this Refermce Manual and the UVM Cookbook.
In reply to chr_sue:
Can you give me URL for that.
In reply to Prawin kumar:
This comes with the UVM Class Library
http://www.accellera.org/downloads/standards/uvm
In reply to chr_sue:
Tq Mr chr_sue,
Can you help on this,
I want write a uvm code for simple logic gate, with inputs of int-a,int_b output is out,
i want to randomize inputs for generation output with uvm components only,
so, i’m unable to randomize those inputs can you check it ones
**http://www.edaplayground.com/x/ttv**
Thanks,
In reply to Prawin kumar:
I don’t have the permission to view the code in EDA-Playground.
In reply to chr_sue:
can you check it now.