In reply to Prawin kumar:
Is the sequence compatible with the sequencer? It looks like it is not. Does the sequence generate the same seq_items as the sequencer is parameterized?
if (!uvm_config_db#(virtual ac_lpc_if)::get(this, "", "vif", vif)) begin
`uvm_fatal("ac_lpc_env", "No virtual interface specified for this env instance")
end
uvm_config_db#(virtual ac_lpc_if)::set( this, "agent", "vif", vif);
endfunction
function void connect_phase(uvm_phase phase);
driver.drv_to_sb.connect(scoreboard.input_fifo.analysis_export);
monitor.item_collected_port.connect(scoreboard.output_fifo.analysis_export);
endfunction
endclass: ac_lpc_env
Why are you creating a driver and monitor (and sequencer?) in your environment? You are creating an agent which should contain these components. In your environment, you should only create the agent and scoreboard.
Because am made connections of driver to scoreboard and monitor to scoreboard in environment only. that’s why am creating agent components in environment also …
we cannot connect components without create right.
The agent will create its own driver, monitor and sequencer. There is no need to create them in the environment. The agent should also have an analysis port, which is connected to the monitor’s analysis port. You will connect the agent’s analysis port to the scoreboard.
A poorly written agent won’t have an analysis port, in which case you will connect the monitor’s analysis port to the scoreboard.
This is what the Refernce Manual says:
Defines standard verbosity levels for reports.
UVM_NONE Report is always printed. Verbosity level setting can not disable it.
UVM_LOW Report is issued if configured verbosity is set to UVM_LOW or above.
UVM_MEDIUM Report is issued if configured verbosity is set to UVM_MEDIUM or above.
UVM_HIGH Report is issued if configured verbosity is set to UVM_HIGH or above.
UVM_FULL Report is issued if configured verbosity is set to UVM_FULL or above.
You should learn fo work with this Refermce Manual and the UVM Cookbook.
I want write a uvm code for simple logic gate, with inputs of int-a,int_b output is out,
i want to randomize inputs for generation output with uvm components only,
so, i’m unable to randomize those inputs can you check it ones
In reply to Prawin kumar:
I can see you code, but it is not really simulating. It proceeds only in time but does not issue any uvm_info with the exception of the build_phase.
Lookin to your code I see strange things in your sequence:
You are randomizing twice. First with the randomize meothod belonging to the classes, which is fine and then randomizing with $urandom, which is not good.
I had a deeper look to your code. You do not understand the UVM build process using the different phases: build_phase, connect_phase.
Passing the virtual interface through your environment is a nightmare. TLM components never have a virtual interface!
Watch the UVM related videos in the Verification Academy, then clean-up and run your code.