UVM_ERROR

UVM
41

In reply to Prawin kumar:
I can see you code, but it is not really simulating. It proceeds only in time but does not issue any uvm_info with the exception of the build_phase.

Lookin to your code I see strange things in your sequence:

    start_item(req);
    assert (req.randomize());
    req.delay = $urandom_range(1, 20);
    req.int_a = $urandom();
    req.int_b =$urandom();
    finish_item(req);

You are randomizing twice. First with the randomize meothod belonging to the classes, which is fine and then randomizing with $urandom, which is not good.

42

In reply to Prawin kumar:

I had a deeper look to your code. You do not understand the UVM build process using the different phases: build_phase, connect_phase.
Passing the virtual interface through your environment is a nightmare. TLM components never have a virtual interface!
Watch the UVM related videos in the Verification Academy, then clean-up and run your code.

43

In reply to chr_sue:

Can you elaborate which is mistake, build phase is very clear and connect phase also

44

In reply to Prawin kumar:

Please look here:

45

In reply to chr_sue:

it randomize only frame 0,but we given i<20 .
and what about signal out?

46

In reply to Prawin kumar:

Your DUT is instantiated, but not connected to the interface.
I did not check all Details. My guess is yout testbench is stucking somewhere in the monitor or the scoreboard.

47

In reply to chr_sue:

I had a closer look to your code. The clock generation did im module top did not work.
I have fixed this. See

48

In reply to chr_sue:

ok chr_sue,

Thank you so much for your support.

We generates the stimulus fine but

with this i want verify the DUT? how can i?

49

In reply to Prawin kumar:

First you have to connect your DUT to the interface in your toplevel module. Then your Environment is complete.
To verify your design you Need sequences and Tests. In your tests you select a certain sequence to verify the features of your design.

50

In reply to chr_sue:

dut dut1 ( .clk(lpc_if.clk),
.reset(lpc_if.reset),
.int_a(lpc_if.int_a),
.int_b(lpc_if.int_b),
.out(lpc_if.out)

          );

i connect the DUT to Vif in top level,

In driver we transfer the stimulus from driver to vif as shown below
vif.int_a = seq.int_a;
vif.int_b = seq.int_b;

from the DUT to monitor am getting an output i.e signal “out”
and scoreboard connection like ‘compare’ not working …

Can you check this …
uvm_gate - EDA Playground

51

In reply to Prawin kumar:

In the monitor you do not extract a Transaction. You are writing an empty Transaction to the Analysis port.

52

In reply to chr_sue:

virtual function void write(sequence_item pkt);
monitor.item_collected_port = vif.int_a
monitor.item_collected_port = vif.int_b
$display(“SCB:: Pkt recived”);
pkt.print();
endfunction : write

am write the write transaction in scoreboard i.e
from virtual interface int_a and int_b writing into the monitor.

is this write???

53

In reply to Prawin kumar:

This is wrong. In the write function you have to define what happens with the extracted transaction.
In the run_phase of the monitor you have to assemble your tarnsaction from the values of the virtual interface.

54

In reply to chr_sue:

OK i understand but in monitor ,

task;
@(vif.clk)
??? = vif.int_a;
??? = vif.int_b;
endtask

  from the above code in ??? place what we mentioned ? there is know specific signal to store int_a and int_b;
55

In your monitor run_phase task you have to declare and construct a Transaction.Assign to the data memebers of this Transaction the corresponding Values from the Virtual interface.
If you have done this you Can write this transaction to the analysis port of your monitor.

56

In reply to chr_sue:

task run_phase(uvm_phase phase);
logic [2:0]in_a;
logic [2:0]in_b;
sequence_item transaction;
transaction = sequence_item::type_id::create(“transaction”);

in_a = vif.int_a;
in_b = vif.int_b;
 @ (vif.clk);
item_collected_port.write(transaction);
`uvm_info("AC_LPC_MONITOR", $psprintf("Wrote transaction %s",transaction.convert2string()), UVM_LOW);

endtask:run_phase

Am coded like this, i had take in_a,in_b type of logic from the vif int_a and int_b trasaction to in_a,in_b.

even though scoreboard not compare this values.

57

In reply to Prawin kumar:

I strongly recommend to watch the videos from the UVM Courses!
You do not understand the TLM - Transaction Level Modelling. But this is key for the UVM.

Your run_phase Task should look like this:

task run_phase(uvm_phase phase);
sequence_item transaction;
transaction = sequence_item::type_id::create("transaction");
forever begin
  @ (vif.clk);
  transaction.in_a = vif.int_a;
  transaction.in_b = vif.int_b;

  item_collected_port.write(transaction);
  `uvm_info("AC_LPC_MONITOR", $psprintf("Wrote transaction %s",transaction.convert2string()), UVM_LOW);
  end
endtask:run_phase
58

In reply to chr_sue:

Yes, i watched the TLM transaction modeling.

i made the changes as per your suggestions
but scoreboard did not take values from components (MON,DRV).

did i made any mistake.

59

In reply to Prawin kumar:
You don’t send data from the driver to the scoreboard.
See the solution here:

60

In reply to chr_sue:

Tq mr chr_sue,

I modified scoreboard with my convince,i want out also with the inputs.
could you please help on this, run the below code and give me some suggestions

uvm_gate - EDA Playground