In reply to Prawin kumar:
See the solution here:
Please note ALL changes I did, also in the design.
In reply to chr_sue:
1 @ (posedge vif.clk);
2 vif.int_a = seq.int_a;
3 vif.int_b = seq.int_b;
4 seq.outp = seq.int_a + seq.int_b;
why are you using line-4 hear, Tb only for stimulus generation purpose, why you using design in TB.
In reply to Prawin kumar:
seq.outp represents the result and works as the refernce model. This data is not driven to the design. I Could do this also in the scoreboard. Where to do this is a question of taste.
In reply to chr_sue:
uvm_test_top.env.agent.driver [ac_lpc_driver] Got Transaction int_a=3 int_b=4
#1 KERNEL: UVM_INFO /home/runner/testbench.sv(182) @ 50: uvm_test_top.env.agent.driver [AC_LPC_DRIVER] transaction int_a=3 int_b=4
#2 KERNEL: UVM_INFO /home/runner/testbench.sv(186) @ 50: uvm_test_top.env.agent.driver [ac_lpc_driver] item_done
#3 KERNEL: UVM_INFO /home/runner/testbench.sv(224) @ 50: uvm_test_top.env.agent.monitor [AC_LPC_MONITOR] Wrote transaction int_a=3 int_b=4 out= 0
I put the “`UVM_INFO” after DRIVER and MONITOR operations
am given inputs to dut(out=int_a + int_b) int=3,int_b=4 in line 1;
from the 2 line says about driver drive the that inputs into VIF i.e int_a=3,int=4; line 2 then,
in case for monitor
monitoring the data after DUT operation ,so int_a=3,int_b=4 displaying properly but out signal displayed as 0 ,from line 3 .
My question is : we are driving the inputs to VIF ,VIF instantiated with DUT in top then, in monitor we monitor inputs and output from VIF right even though it displaying output as “zero” .
In reply to Prawin kumar:
What you see is correct. @50 is the first edge of your clock. At that time the output from the DUT is not updated. It is still 0.
You are working on both clock edges. Is this your intention?
Please review in detail my solution I have provided to you!
In reply to chr_sue:
Hi chr_sue,
Finally i designed the code as per my requirements means how the my output displayed i.e ACTUAL and EXPECTED values ,
So,finally i got the solution for that with your great support.
Thanks,
Prawin
In reply to Prawin kumar:
What isStart of simulation and end of elaboration phases ??
Can i implement in my uvm code ?
Thanks,
Prawin
In reply to Prawin kumar:
start_of_simulation_phase and end_of_elobotation_phase are predefined phases in the UVM
In reply to Prawin kumar:
It is not a good solution to have functional coverage inside the monitor. Create a seperate coverage collector component and connet this to the analysis port of the monitor.
Best is to use as baseclas for the coverage collector uvm_subscriber.