In reply to Prawin kumar:
I can see you code, but it is not really simulating. It proceeds only in time but does not issue any uvm_info with the exception of the build_phase.
Lookin to your code I see strange things in your sequence:
You are randomizing twice. First with the randomize meothod belonging to the classes, which is fine and then randomizing with $urandom, which is not good.
I had a deeper look to your code. You do not understand the UVM build process using the different phases: build_phase, connect_phase.
Passing the virtual interface through your environment is a nightmare. TLM components never have a virtual interface!
Watch the UVM related videos in the Verification Academy, then clean-up and run your code.
Your DUT is instantiated, but not connected to the interface.
I did not check all Details. My guess is yout testbench is stucking somewhere in the monitor or the scoreboard.
First you have to connect your DUT to the interface in your toplevel module. Then your Environment is complete.
To verify your design you Need sequences and Tests. In your tests you select a certain sequence to verify the features of your design.
This is wrong. In the write function you have to define what happens with the extracted transaction.
In the run_phase of the monitor you have to assemble your tarnsaction from the values of the virtual interface.
In your monitor run_phase task you have to declare and construct a Transaction.Assign to the data memebers of this Transaction the corresponding Values from the Virtual interface.
If you have done this you Can write this transaction to the analysis port of your monitor.
I strongly recommend to watch the videos from the UVM Courses!
You do not understand the TLM - Transaction Level Modelling. But this is key for the UVM.