UVM_ERROR

In reply to cgales:

Thank you cgales

In reply to Prawin kumar:

Hi,

What is verbosity of UVM_INFO in uvm monitor.

i.e deference between UVM_LOW,UVM_HIGH,UVM_NONE,UVM_MEDIUM.

Thanks,

In reply to Prawin kumar:

This is what the Refernce Manual says:
Defines standard verbosity levels for reports.
UVM_NONE Report is always printed. Verbosity level setting can not disable it.
UVM_LOW Report is issued if configured verbosity is set to UVM_LOW or above.
UVM_MEDIUM Report is issued if configured verbosity is set to UVM_MEDIUM or above.
UVM_HIGH Report is issued if configured verbosity is set to UVM_HIGH or above.
UVM_FULL Report is issued if configured verbosity is set to UVM_FULL or above.

You should learn fo work with this Refermce Manual and the UVM Cookbook.

In reply to chr_sue:

Can you give me URL for that.

In reply to Prawin kumar:

This comes with the UVM Class Library
http://www.accellera.org/downloads/standards/uvm

In reply to chr_sue:

Tq Mr chr_sue,

Can you help on this,

I want write a uvm code for simple logic gate, with inputs of int-a,int_b output is out,
i want to randomize inputs for generation output with uvm components only,

so, i’m unable to randomize those inputs can you check it ones

   **http://www.edaplayground.com/x/ttv**   

Thanks,

In reply to Prawin kumar:

I don’t have the permission to view the code in EDA-Playground.

In reply to chr_sue:

can you check it now.

In reply to Prawin kumar:
I can see you code, but it is not really simulating. It proceeds only in time but does not issue any uvm_info with the exception of the build_phase.

Lookin to your code I see strange things in your sequence:

    start_item(req);
    assert (req.randomize());
    req.delay = $urandom_range(1, 20);
    req.int_a = $urandom();
    req.int_b =$urandom();
    finish_item(req);

You are randomizing twice. First with the randomize meothod belonging to the classes, which is fine and then randomizing with $urandom, which is not good.

In reply to Prawin kumar:

I had a deeper look to your code. You do not understand the UVM build process using the different phases: build_phase, connect_phase.
Passing the virtual interface through your environment is a nightmare. TLM components never have a virtual interface!
Watch the UVM related videos in the Verification Academy, then clean-up and run your code.

In reply to chr_sue:

Can you elaborate which is mistake, build phase is very clear and connect phase also

In reply to Prawin kumar:

Please look here:

In reply to chr_sue:

it randomize only frame 0,but we given i<20 .
and what about signal out?

In reply to Prawin kumar:

Your DUT is instantiated, but not connected to the interface.
I did not check all Details. My guess is yout testbench is stucking somewhere in the monitor or the scoreboard.

In reply to chr_sue:

I had a closer look to your code. The clock generation did im module top did not work.
I have fixed this. See

In reply to chr_sue:

ok chr_sue,

Thank you so much for your support.

We generates the stimulus fine but

with this i want verify the DUT? how can i?

In reply to Prawin kumar:

First you have to connect your DUT to the interface in your toplevel module. Then your Environment is complete.
To verify your design you Need sequences and Tests. In your tests you select a certain sequence to verify the features of your design.

In reply to chr_sue:

dut dut1 ( .clk(lpc_if.clk),
.reset(lpc_if.reset),
.int_a(lpc_if.int_a),
.int_b(lpc_if.int_b),
.out(lpc_if.out)

          );

i connect the DUT to Vif in top level,

In driver we transfer the stimulus from driver to vif as shown below
vif.int_a = seq.int_a;
vif.int_b = seq.int_b;

from the DUT to monitor am getting an output i.e signal “out”
and scoreboard connection like ‘compare’ not working …

Can you check this …
uvm_gate - EDA Playground

In reply to Prawin kumar:

In the monitor you do not extract a Transaction. You are writing an empty Transaction to the Analysis port.

In reply to chr_sue:

virtual function void write(sequence_item pkt);
monitor.item_collected_port = vif.int_a
monitor.item_collected_port = vif.int_b
$display(“SCB:: Pkt recived”);
pkt.print();
endfunction : write

am write the write transaction in scoreboard i.e
from virtual interface int_a and int_b writing into the monitor.

is this write???