In reply to tirumalrao_m:
Correct. Use my testbench model http://systemverilog.us/m_rose.sv (with the constrained-random tests (i.e., the randomized)) and verify that it is working as you think it should. You can modify the constraints to tune the testbench.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to ben@SystemVerilog.us:
I tried to run that file as it is, it is not running as it needs uvm package.
I ma not using uvm, just system verilog for my env.
Let me try.
In reply to tirumalrao_m:
Try the following code: http://systemverilog.us/m_roseB.sv
You don’t need uvm; I just used it for the messaging. You can use $error.
module m_rose;
bit clk, a, b;
bit[3:0] delay=6;
int cycle=0;
let VACUOUSOFF = 11; // assertion control type
initial begin
$assertpasson(0);
$assertcontrol( VACUOUSOFF); //
end
always @(posedge clk) cycle <= cycle +1'b1;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
// I want to check b rose 6 cycle after a raises,
// and during 6 cycle b should be zero, should not toggle.
property p_delay;
int v;
($rose(a), v=delay+1'b1, $display("Cycle=%d, START, time=%t, DELAY= %d", cycle, $time, delay)) |->
(v>0 && !b, v=v-1'b1)[*0:$] ##1 v==0 ##0 $rose(b);
endproperty
ap_delay: assert property(p_delay) $display("Cycle=%d, PASS", $sampled(cycle));
else $display("Cycle=%d, FAIL", $sampled(c
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to ben@SystemVerilog.us:
ncsim: *E,MSSYSTF (./test_2.sv,8|14): User Defined system task or function ($assertpasson) registered during elaboration and used within the simulation has not been registered during simulation.
$assertcontrol( VACUOUSOFF); //
I am getting above error.
In reply to tirumalrao_m:
This forum’s emphasis in on language usage and purposely avoids addressing tool issues, as those should be addressed directly with the vendor.
On this particular note, my guess is that the simulator was commanded (or started) into an optimized mode versus a debug mode. You typically do not want to slow the simulator with lots of messages, particularly on PASSONs.
Ben Cohen
http://www.systemverilog.us/
In reply to ben@SystemVerilog.us:
Hi ,
Thanks a lot for you solutions.
below code works for me.
property seq_a_b(a,sclk,b,delay);
int v,v2;
@(a or posedge sclk)
(rose(a), v=delay+1'b1) |-> (v>0 && !b, v=v-1'b1)[*0:] ##1 v==0 ##0 $rose(b);
endproperty : seq_a_b
Seems interesting topic. Is there any simple way to check signal pipeline variable delay. let’s consider 2 signals x1 and x2. Here x2 is delayed version on x1 and this delay is programmable with some variable. I don’t want to check value or state of x2 based on change on x1 because it may possible that x2 follows all transaction on x1 but there are also unexpected transaction x2 that are not there on x1 those transition also needs to be reported as error.
In reply to Digesh:
Seems interesting topic. Is there any simple way to check signal pipeline variable delay. let’s consider 2 signals x1 and x2. Here x2 is delayed version on x1 and this delay is programmable with some variable. I don’t want to check value or state of x2 based on change on x1 because it may possible that x2 follows all transaction on x1 but there are also unexpected transaction x2 that are not there on x1 those transition also needs to be reported as error.
You need to first clarify your requirements about the relationships between x1 and x2.
Once this is done, you can easily write assertions. Understand your requirements!
:)
Ben Cohen SystemVerilog.us
In reply to ben@SystemVerilog.us:
In reply to Digesh:
You need to first clarify your requirements about the relationships between x1 and x2.
Once this is done, you can easily write assertions. Understand your requirements!
:)
Ben Cohen SystemVerilog.us
x2 always follows x1 is normal condition. 2 transition on x1 before they reach x2 is also normal condition in such condition you should expect same 2 transition on x2. Now if you think of error behavior it can be like you said 2 occurrences of x2 after x1 other error condition I think of are :
Please let me know if you are having hard time understanding my point. I can draw some diagram that way you it will be easy for you to understand me.
In reply to Digesh:
In reply to ben@SystemVerilog.us:
x2 always follows x1 is normal condition. 2 transition on x1 before they reach x2 is also normal condition in such condition you should expect same 2 transition on x2. Now if you think of error behavior it can be like you said 2 occurrences of x2 after x1 other error condition I think of are :
I’ll give you guidelines in writing the needed assertions.
Ben Cohen
In reply to ben@SystemVerilog.us:
In reply to Digesh:
I’ll give you guidelines in writing the needed assertions.
Ben Cohen
Hi Ben ,
Thanks for reply I have already implemented this check as per below.
property pipe_dly_chk(clk,rst,variable,signal1,signal2);
int v_b;
@(clk) disable iff(rst)
if(variable == 0)
(($changed(signal1))|-> (signal2 == signal1))
else
(($changed(signal1), v_b=signal1) |->(pipe_dly_seq(variable,1)) |-> (signal2 == v_b ));
endproperty : pipe_dly_chk
sequence pipe_dly_seq(max_count, expr);
integer count;
(expr,count = max_count) ##0 (count > 0,count = count - 1)[*0:$] ##1 (count == 0);
endsequence :pipe_dly_seq
DELAY_CHK : assert property (pipe_dly_chk(clk,enable_condition,(2 * delay_depth_in_terms_of_clk),signal1,signal2))
else
error_msg
always @(signal1)begin
sig1_cnt = sig1_cnt + 1;
end
always @(signal2)begin
sig2_cnt = sig2_cnt + 1;
end
final begin
if(enable_condition)begin
CNT_CHK: assert (sig1_cnt == sig2_cnt) else $display(“sig1_cnt:%d and sig2_cnt:%d count mismatch”,sig1_cnt,sig2_cnt);
end
end
Let me know if you think of any better solution than this.
In reply to Digesh:
You need to build a testbench for the assertions and see if it meets your requirements.
As you may have noticed, I typically use the randomize with weighted distributions to generate the test signals. For example:
import uvm_pkg::*; `include "uvm_macros.svh"
module m;
bit clk, a, din;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
initial begin
repeat(200) begin
@(posedge clk);
if (!randomize(a, din) with
{ a dist {1'b1:=1, 1'b0:=3};
din dist {1'b1:=1, 1'b0:=2};
}) `uvm_error("MYERR", "This is a randomize error")
end
$finish;
end
endmodule
In my 4th edition of the SVA book, I have a chapter thta addresses building a testbench for assertions, and explain the use of typical constraints.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
What if the requirement is to pass a range of delay as input variables? For example in the following assertion
$rose (sigA) |-> ##[min_cycle_response:max_cycle_response] ($fell(sigB)) ;
passing delay as parameters from the module seem to work. Is there another way or are there any disadvantage using parameter instead of input ?
Example:
module event_sigA_assertion #(parameter int min_cycle_response=0,max_cycle_response=0 )
(
input ref_clk,
input assert_enable,
input sigA,
input sigB
);
property p_event_clear_reset_assert;
@(posedge ref_clk)
disable iff (!assert_enable)
$rose (sigA) |-> ##[min_cycle_response:max_cycle_response] ($fell(sigB)) ;
endproperty
endmodule
If the 2 ranges (min and max) are small, you can use the generate with 2 loops that will create multiple assertions. You can also use a property with local variables; that can be tricky, but the following looks OK to me.
import uvm_pkg::*; `include "uvm_macros.svh"
module m5067;
parameter N=0; // <--- Parameter, used for testing a simple assertion
bit clk, a, b, c;
bit[2:0] v=3, v0=0, v1=3;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
// ap_range: assert property($rose(a) |-> ##[v0:v1] b); // WANT
ap_range_fix: assert property($rose(a) |-> ##[N:3] b); // Simple, fixd range
property p_range_equivalent; // Equivalent implementation
// Range defined by module variables v0 and v1
int lv0, lv1; // this is an internal local variable defined by the tool
($rose(a), lv0=v0, lv1=v1 )
|->
##0 first_match((1'b1, lv0=lv0-1'b1, lv1=lv1- 1'b1) [*0:$] ##1 lv0<=0)
##0 first_match( (1, lv1=lv1- 1'b1)[*0:$] ##1 (b || lv1<=0))
##0 b;
endproperty
ap_range_equivalent: assert property(p_range_equivalent);
initial begin // Testing of assertions
repeat(200) begin
@(posedge clk);
#1 if (!randomize(a, b, c) with
{ a dist {1'b1:=1, 1'b0:=5};
b dist {1'b1:=10, 1'b0:=4};
c dist {1'b1:=3, 1'b0:=1};})
`uvm_error("MYERR", "This is a randomize error")
end
$finish;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to ben@SystemVerilog.us:
In reply to Elbosily:
Some comments
// 1) Following assertion can never fail because if the *0:$] and b==0
($rose(a), v=delay+1'b1) |-> (v>0, v=v-1'b1)[*0:$] ##1 v==0 ##0 b == 1;
// 2) Following assertion CAN fail because of the first_match() if b==0
($rose(a), v=delay+1'b1) |->
first_match((v>0, v=v-1'b1)[*0:$] ##1 v==0) ##0 b == 1;
// 3) Consider the following example
int v=5;
ap_1: assert property( x|-> ##2 b ##v c); // illegal in 1800'2012
/* If the variable used to define the delay has values that are within a constraint
range, such as between 0 and 7 (or 15, or at most 32) one can use the generate statement, which appears much simpler than the use of local variables and the sequence_match_item. Example: */
generate for (genvar g_i=0; g_i<8; g_i++) begin
ap_delay_gen: assert property (v==g_i && $rose(a) |-> ##g_i b);
end endgenerate
// 4) When a parameter is used, the value is static (and does not change) after elaboration, prior to sim.
Ben SystemVerilog.us
Hello Ben,
I am a big fan of you. Your way of solving problems via SVA is amazing. I have a question:
If the variable delay can be achieved by passing parameters then why do we need to do this lengthy workaround?
I’ll be looking forward to your humble response.
Thank you,
Regards,
Muneeb Ulla Shariff
In reply to muneebullashariff:
Parameters work because they are static after elaboration.
I am not trying to stop you from asking questions, but one good advice that was given to me was to test certain theories or problems to better understand the legality of code.
You your specific question on parameters, see my example at
Thanks for being a “fan”
:)
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to ben@SystemVerilog.us:
In reply to muneebullashariff:
Parameters work because they are static after elaboration.
I am not trying to stop you from asking questions, but one good advice that was given to me was to test certain theories or problems to better understand the legality of code.
You your specific question on parameters, see my example at
Edit code - EDA Playground
Thanks for being a “fan”
:)
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
Hey Ben,
Many thanks for your reply. I ran the code on edaplayground and got a good feel of the problem. However, I do have a question:
In what scenarios do we need to use parameterized delays and when do we need to use this variable delay (workaround)?
Thank you,
Regards,
Muneeb Ulla Shariff
In reply to muneebullashariff:
In what scenarios do we need to use parameterized delays and when do we need to use this variable delay (workaround)?
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to ben@SystemVerilog.us:
Is it possible to use a variable along with $past construct ?
property sig_high_check;
int high_value;
@(posedge clk)
($rose(signal_b), high_value = signal_a_reg) |-> $past($rose(signal_a),high_value);
endproperty
Throws error - variable can’t use along with $past.