In reply to ben@SystemVerilog.us:
I tried to run that file as it is, it is not running as it needs uvm package.
I ma not using uvm, just system verilog for my env.
Let me try.
In reply to ben@SystemVerilog.us:
I tried to run that file as it is, it is not running as it needs uvm package.
I ma not using uvm, just system verilog for my env.
Let me try.