In reply to ben@SystemVerilog.us:
In reply to muneebullashariff:
Parameters work because they are static after elaboration.
I am not trying to stop you from asking questions, but one good advice that was given to me was to test certain theories or problems to better understand the legality of code.
You your specific question on parameters, see my example at
Edit code - EDA Playground
Thanks for being a “fan”
:)
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
Hey Ben,
Many thanks for your reply. I ran the code on edaplayground and got a good feel of the problem. However, I do have a question:
In what scenarios do we need to use parameterized delays and when do we need to use this variable delay (workaround)?
Thank you,
Regards,
Muneeb Ulla Shariff