If the 2 ranges (min and max) are small, you can use the generate with 2 loops that will create multiple assertions. You can also use a property with local variables; that can be tricky, but the following looks OK to me.
import uvm_pkg::*; `include "uvm_macros.svh"
module m5067;
parameter N=0; // <--- Parameter, used for testing a simple assertion
bit clk, a, b, c;
bit[2:0] v=3, v0=0, v1=3;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
// ap_range: assert property($rose(a) |-> ##[v0:v1] b); // WANT
ap_range_fix: assert property($rose(a) |-> ##[N:3] b); // Simple, fixd range
property p_range_equivalent; // Equivalent implementation
// Range defined by module variables v0 and v1
int lv0, lv1; // this is an internal local variable defined by the tool
($rose(a), lv0=v0, lv1=v1 )
|->
##0 first_match((1'b1, lv0=lv0-1'b1, lv1=lv1- 1'b1) [*0:$] ##1 lv0<=0)
##0 first_match( (1, lv1=lv1- 1'b1)[*0:$] ##1 (b || lv1<=0))
##0 b;
endproperty
ap_range_equivalent: assert property(p_range_equivalent);
initial begin // Testing of assertions
repeat(200) begin
@(posedge clk);
#1 if (!randomize(a, b, c) with
{ a dist {1'b1:=1, 1'b0:=5};
b dist {1'b1:=10, 1'b0:=4};
c dist {1'b1:=3, 1'b0:=1};})
`uvm_error("MYERR", "This is a randomize error")
end
$finish;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115