Need to Use Variable in Assertions ## Delay

In reply to tirumalrao_m:
This forum’s emphasis in on language usage and purposely avoids addressing tool issues, as those should be addressed directly with the vendor.
On this particular note, my guess is that the simulator was commanded (or started) into an optimized mode versus a debug mode. You typically do not want to slow the simulator with lots of messages, particularly on PASSONs.
Ben Cohen
http://www.systemverilog.us/

  • SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448