Need to Use Variable in Assertions ## Delay

SystemVerilog
21

In reply to tirumalrao_m:

Correct. Use my testbench model http://systemverilog.us/m_rose.sv (with the constrained-random tests (i.e., the randomized)) and verify that it is working as you think it should. You can modify the constraints to tune the testbench.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448