In reply to Digesh:
In reply to ben@SystemVerilog.us:
x2 always follows x1 is normal condition. 2 transition on x1 before they reach x2 is also normal condition in such condition you should expect same 2 transition on x2. Now if you think of error behavior it can be like you said 2 occurrences of x2 after x1 other error condition I think of are :
- transition on x2 only
- transition on x1 only
- n number of transition on x1 but m transition on x2 where (m !== n)
I’ll give you guidelines in writing the needed assertions.
- FOR “2 transition on x1 before they reach x2 is also normal condition in such condition you should expect same 2 transition on x2”, see my solution with the use of ticket, now_serving.
Counting number of events on clock a, while clock o is forbidden - SystemVerilog - Verification Academy - FOR “n number of transition on x1 but m transition on x2 where (m !== n)”, you can use the module variables int ticket, now_serving as the difference should be zero at the end of simulation, or at times determined by you.
- FOR “2 occurrences of x2 after x1 // Error behavior”. Use something like
rose(x1) |-> strong(x2[->1] ##1 !x2[*0:] ##1 $rose(x1));
BTW, this is in conflict with your first requirement “2 transition on x1 before they reach x2”
Ben Cohen