How to pass an interface in checker.. endchecker block argument?

SystemVerilog
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1

Hi All,

I want to pass an entire interface from my testbench’s top module to the checker…endchecker block. Is it possible to do so?

2

In reply to atanu.biswas:

Hi All,
I want to pass an entire interface from my testbench’s top module to the checker…endchecker block. Is it possible to do so?

You need to read 1800’2017 17.2 Checker declaration


checker checker_identifier [ ( [ checker_port_list ] ) ] ;
{ { attribute_instance } checker_or_generate_item }
endchecker [ : checker_identifier ]
checker_port_list ::= // from A.1.8
checker_port_item {, checker_port_item}
checker_port_item ::=
{ attribute_instance } [ checker_port_direction ] property_formal_type formal_port_identifier
{variable_dimension} [ = property_actual_arg ]

property_port_item ::=
{ attribute_instance } [ local [ property_lvar_port_direction ] ] property_formal_type
formal_port_identifier {variable_dimension} [ = property_actual_arg ]

// What this says is that in an checker, Interfaces and wires are NOT in the formal argument
// Also, per 1800 
"Modules, interfaces, programs, and packages shall not be declared inside checkers. Modules, interfaces, and programs shall not be instantiated inside checkers."

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  1. SVA Alternative for Complex Assertions
    https://verificationacademy.com/news/verification-horizons-march-2018-issue
  2. SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  3. SVA in a UVM Class-based Environment
    https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
3

In reply to ben@SystemVerilog.us:

Hello Ben,

Thanks for the reply. I understood that. There is one more question. Can we define parameters in Checker block like we do for modules?

4

In reply to atanu.biswas:

If not possible to pass parameters to checker block, Can you suggest some other alternative?

5

In reply to atanu.biswas:
The following works


let MSB=3; let LSB=0;
let DEPTH=8;
let FIFO_MSB = DEPTH*MSB;
let FIFO_LSB = LSB;
checker generic_fifo
    // #(MSB=3, LSB=0) //   ILLEGAL
    (input bit [MSB:LSB] in,
    input bit clk, read, write, reset,
    output logic [MSB:LSB] out,
    output logic full, empty );  
    //parameter DEPTH=4; //ILLEGAL  
endchecker

BTW, from my SVA book, The following table provides an overview of where checkers are declared, used, and their contents.

419×570 71.3 KB

419×570 71.3 KB

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home

  1. SVA Alternative for Complex Assertions
    https://verificationacademy.com/news/verification-horizons-march-2018-issue
  2. SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  3. SVA in a UVM Class-based Environment
    https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
6

In reply to ben@SystemVerilog.us:

Hi Ben,

Thanks for suggesting that. I need to create multiple instance of the checker in my top module and for each instance the parameter is different. Can the let variable be overridden as was the case with parameters? Also is it legal to assign an input formal argument of the checker to the let variable as shown below?

checker ( input bit [3:0] no_of_bits_to_compare );

let WIDTH = no_of_bits_to_compare;

endchecker

The “WIDTH” is going to be used in an assertion property.

7

In reply to atanu.biswas:

In reply to ben@SystemVerilog.us:
Thanks for suggesting that. I need to create multiple instance of the checker in my top module and for each instance the parameter is different. Can the let variable be overridden as was the case with parameters?

See 1800’2017 11.12 Let construct
One fast way to verify the legality of construct is to try it using a simulator; hopefully, the tool undestands the syntax better than we do :).
Redeclaring the let defintion in the same context (e.g., in the same module) is illegal.

Also is it legal to assign an input formal argument of the checker to the let variable as shown below?
checker ( input bit [3:0] no_of_bits_to_compare );
let WIDTH = no_of_bits_to_compare;
endchecker
The “WIDTH” is going to be used in an assertion property.

This looks very convoluted and hard to follow. Looks like you want to define a let_definition to a checker variable that can dynamically change in value during simulation. You then want to use that definition as a range value in an assertion. ranges and repeasts in properties have to be static, and cannot be dynamic.

Question: Why are you using a checker? If the assertions defined in a checker are instantiated in-place within a module (i.e., are not instantiated inside an always block in the module), then you might as well use module instead of checker.
Since the instantiated verification modules should not be synthesized, use the NO_SYNTHESIS pragma around that instantiation. Check the syntax for the pragma.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  1. SVA Alternative for Complex Assertions
    https://verificationacademy.com/news/verification-horizons-march-2018-issue
  2. SVA: Package for dynamic and range delays and repeats - SystemVerilog - Verification Academy
  3. SVA in a UVM Class-based Environment
    https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
8

In reply to ben@SystemVerilog.us:

Hello Ben,

That was informative. I understood that. Thank you.

9

In reply to ben@SystemVerilog.us:

Hi Ben,

I have a doubt. The image says that assign statement cannot be used inside a checker body. But I have used an assign statement inside my checker block out of sheer curiosity to check how it behaves or what kind of error it throws. But surprisingly its working fine. Below is the code:

checker reg_check ( input logic [31:0] address );

logic write_cycle;

assign write_cycle = (top.mst_p.PADDR = address) && top.mst_p.PWRITE && top.mst_p.PENABLE && top.mst_p.PSEL;

endchecker

The toggling of the write_cycle is happening correctly.

10

In reply to atanu.biswas:
You are correct in that continuous assignments are legal in a checker, my error since I did not revise that point from my 3rd Edition where it was illegal in the previous version of 1800. Thanks for pointing that out.


// 1800'2017 17.2 Checker declaration
checker checker_identifier [ ( [ checker_port_list ] ) ] ;
{ { attribute_instance } checker_or_generate_item }
endchecker [ : checker_identifier ]

checker_or_generate_item ::=
checker_or_generate_item_declaration
| initial_construct
| always_construct
| final_construct
| assertion_item
| continuous_assign      // <---------
| checker_generate_item

Ben SystemVerilog.us

11

In reply to ben@SystemVerilog.us:

Hi Ben,

Thanks a lot for confirming this. I have one more query. In my checker block I am having a UVM RAL based functionality. The code is as follows:

Checker block code:
checker reg_check(input string reg_name);
logic [31:0] address;
logic write_cycle;

initial begin
top.reg_temp = top.ral_inst.get_reg_by_name(reg_name);
address = top.reg_temp.get_address();
end

assign write_cycle = (top.mst_p.PADDR = address) && top.mst_p.PWRITE && top.mst_p.PENABLE && top.mst_p.PSEL;

endchecker

Top module code:
module top;

reg_block ral_inst;
uvm_reg reg_temp;

initial begin
ral_inst = reg_block::type_id::create(“ral_inst”);
ral_inst.build();
ral_inst.compare;
end

//Checker instance
reg_check rg3 (“register_name”);

endmodule

The issue is that I am getting a warning which reads:
**** Warning: (vsim-2974) Cannot find checker decl ‘reg_check’ for checker instance rg3**

Although the checker is working completely fine.

12

In reply to atanu.biswas:

Checkers cannot make references to dynamic variables.
In the checker you have:
top.reg_temp = top.ral_inst.get_reg_by_name(reg_name);

In the module you have:
ral_inst = reg_block::type_id::create(“ral_inst”);
That’s from a class, dynamic in nature.

Again, this forum doez not address specific tools.
You tool error message should have been relayed without the identity of the tool, and more in a generic sense, like
A tool reported that it Cannot find checker decl ‘reg_check’ for checker instance rg3

Ben systemverilog.us

13

In reply to ben@SystemVerilog.us:

Understood. Thanks.

In reply to atanu.biswas:
Again, this forum doez not address specific tools.
You tool error message should have been relayed without the identity of the tool, and more in a generic sense, like
A tool reported that it Cannot find checker decl ‘reg_check’ for checker instance rg3
Ben systemverilog.us

I got it Ben. Will take care of it from next time.